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https://github.com/brain-hackers/u-boot-brain
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99b0f0fd3f
Change the xilinx device drivers and board code to include config.h instead of xparameters.h directly. config.h always includes the correct xparameters file. This change reduces the posibility of including the wrong file when adding a new xilinx board port Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
674 lines
27 KiB
C
674 lines
27 KiB
C
/******************************************************************************
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*
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* Author: Xilinx, Inc.
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
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* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
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* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
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* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
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* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
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* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
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* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
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* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
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* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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* Xilinx hardware products are not intended for use in life support
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* appliances, devices, or systems. Use in such applications is
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* expressly prohibited.
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*
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*
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* (c) Copyright 2002-2004 Xilinx Inc.
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* All rights reserved.
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*
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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*
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* @file xemac.h
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*
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* The Xilinx Ethernet driver component. This component supports the Xilinx
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* Ethernet 10/100 MAC (EMAC).
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*
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* The Xilinx Ethernet 10/100 MAC supports the following features:
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* - Simple and scatter-gather DMA operations, as well as simple memory
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* mapped direct I/O interface (FIFOs).
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* - Media Independent Interface (MII) for connection to external
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* 10/100 Mbps PHY transceivers.
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* - MII management control reads and writes with MII PHYs
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* - Independent internal transmit and receive FIFOs
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* - CSMA/CD compliant operations for half-duplex modes
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* - Programmable PHY reset signal
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* - Unicast, broadcast, and promiscuous address filtering (no multicast yet)
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* - Internal loopback
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* - Automatic source address insertion or overwrite (programmable)
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* - Automatic FCS insertion and stripping (programmable)
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* - Automatic pad insertion and stripping (programmable)
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* - Pause frame (flow control) detection in full-duplex mode
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* - Programmable interframe gap
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* - VLAN frame support.
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* - Pause frame support
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*
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* The device driver supports all the features listed above.
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*
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* <b>Driver Description</b>
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*
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* The device driver enables higher layer software (e.g., an application) to
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* communicate to the EMAC. The driver handles transmission and reception of
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* Ethernet frames, as well as configuration of the controller. It does not
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* handle protocol stack functionality such as Link Layer Control (LLC) or the
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* Address Resolution Protocol (ARP). The protocol stack that makes use of the
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* driver handles this functionality. This implies that the driver is simply a
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* pass-through mechanism between a protocol stack and the EMAC. A single device
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* driver can support multiple EMACs.
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*
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* The driver is designed for a zero-copy buffer scheme. That is, the driver will
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* not copy buffers. This avoids potential throughput bottlenecks within the
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* driver.
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*
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* Since the driver is a simple pass-through mechanism between a protocol stack
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* and the EMAC, no assembly or disassembly of Ethernet frames is done at the
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* driver-level. This assumes that the protocol stack passes a correctly
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* formatted Ethernet frame to the driver for transmission, and that the driver
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* does not validate the contents of an incoming frame
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*
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* <b>PHY Communication</b>
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*
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* The driver provides rudimentary read and write functions to allow the higher
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* layer software to access the PHY. The EMAC provides MII registers for the
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* driver to access. This management interface can be parameterized away in the
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* FPGA implementation process. If this is the case, the PHY read and write
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* functions of the driver return XST_NO_FEATURE.
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*
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* External loopback is usually supported at the PHY. It is up to the user to
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* turn external loopback on or off at the PHY. The driver simply provides pass-
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* through functions for configuring the PHY. The driver does not read, write,
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* or reset the PHY on its own. All control of the PHY must be done by the user.
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*
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* <b>Asynchronous Callbacks</b>
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*
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* The driver services interrupts and passes Ethernet frames to the higher layer
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* software through asynchronous callback functions. When using the driver
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* directly (i.e., not with the RTOS protocol stack), the higher layer
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* software must register its callback functions during initialization. The
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* driver requires callback functions for received frames, for confirmation of
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* transmitted frames, and for asynchronous errors.
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*
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* <b>Interrupts</b>
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*
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* The driver has no dependencies on the interrupt controller. The driver
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* provides two interrupt handlers. XEmac_IntrHandlerDma() handles interrupts
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* when the EMAC is configured with scatter-gather DMA. XEmac_IntrHandlerFifo()
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* handles interrupts when the EMAC is configured for direct FIFO I/O or simple
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* DMA. Either of these routines can be connected to the system interrupt
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* controller by the user.
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*
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* <b>Interrupt Frequency</b>
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*
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* When the EMAC is configured with scatter-gather DMA, the frequency of
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* interrupts can be controlled with the interrupt coalescing features of the
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* scatter-gather DMA engine. The frequency of interrupts can be adjusted using
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* the driver API functions for setting the packet count threshold and the packet
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* wait bound values.
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*
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* The scatter-gather DMA engine only interrupts when the packet count threshold
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* is reached, instead of interrupting for each packet. A packet is a generic
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* term used by the scatter-gather DMA engine, and is equivalent to an Ethernet
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* frame in our case.
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*
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* The packet wait bound is a timer value used during interrupt coalescing to
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* trigger an interrupt when not enough packets have been received to reach the
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* packet count threshold.
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*
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* These values can be tuned by the user to meet their needs. If there appear to
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* be interrupt latency problems or delays in packet arrival that are longer than
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* might be expected, the user should verify that the packet count threshold is
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* set low enough to receive interrupts before the wait bound timer goes off.
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*
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* <b>Device Reset</b>
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*
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* Some errors that can occur in the device require a device reset. These errors
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* are listed in the XEmac_SetErrorHandler() function header. The user's error
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* handler is responsible for resetting the device and re-configuring it based on
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* its needs (the driver does not save the current configuration). When
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* integrating into an RTOS, these reset and re-configure obligations are
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* taken care of by the Xilinx adapter software if it exists for that RTOS.
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*
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* <b>Device Configuration</b>
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*
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* The device can be configured in various ways during the FPGA implementation
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* process. Configuration parameters are stored in the xemac_g.c files.
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* A table is defined where each entry contains configuration information
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* for an EMAC device. This information includes such things as the base address
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* of the memory-mapped device, the base addresses of IPIF, DMA, and FIFO modules
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* within the device, and whether the device has DMA, counter registers,
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* multicast support, MII support, and flow control.
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*
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* The driver tries to use the features built into the device. So if, for
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* example, the hardware is configured with scatter-gather DMA, the driver
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* expects to start the scatter-gather channels and expects that the user has set
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* up the buffer descriptor lists already. If the user expects to use the driver
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* in a mode different than how the hardware is configured, the user should
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* modify the configuration table to reflect the mode to be used. Modifying the
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* configuration table is a workaround for now until we get some experience with
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* how users are intending to use the hardware in its different configurations.
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* For example, if the hardware is built with scatter-gather DMA but the user is
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* intending to use only simple DMA, the user either needs to modify the config
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* table as a workaround or rebuild the hardware with only simple DMA. The
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* recommendation at this point is to build the hardware with the features you
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* intend to use. If you're inclined to modify the table, do so before the call
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* to XEmac_Initialize(). Here is a snippet of code that changes a device to
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* simple DMA (the hardware needs to have DMA for this to work of course):
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* <pre>
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* XEmac_Config *ConfigPtr;
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*
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* ConfigPtr = XEmac_LookupConfig(DeviceId);
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* ConfigPtr->IpIfDmaConfig = XEM_CFG_SIMPLE_DMA;
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* </pre>
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*
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* <b>Simple DMA</b>
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*
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* Simple DMA is supported through the FIFO functions, FifoSend and FifoRecv, of
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* the driver (i.e., there is no separate interface for it). The driver makes use
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* of the DMA engine for a simple DMA transfer if the device is configured with
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* DMA, otherwise it uses the FIFOs directly. While the simple DMA interface is
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* therefore transparent to the user, the caching of network buffers is not.
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* If the device is configured with DMA and the FIFO interface is used, the user
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* must ensure that the network buffers are not cached or are cache coherent,
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* since DMA will be used to transfer to and from the Emac device. If the device
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* is configured with DMA and the user really wants to use the FIFOs directly,
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* the user should rebuild the hardware without DMA. If unable to do this, there
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* is a workaround (described above in Device Configuration) to modify the
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* configuration table of the driver to fake the driver into thinking the device
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* has no DMA. A code snippet follows:
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* <pre>
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* XEmac_Config *ConfigPtr;
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*
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* ConfigPtr = XEmac_LookupConfig(DeviceId);
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* ConfigPtr->IpIfDmaConfig = XEM_CFG_NO_DMA;
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* </pre>
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*
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* <b>Asserts</b>
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*
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* Asserts are used within all Xilinx drivers to enforce constraints on argument
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* values. Asserts can be turned off on a system-wide basis by defining, at
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* compile time, the NDEBUG identifier. By default, asserts are turned on and it
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* is recommended that users leave asserts on during development.
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*
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* <b>Building the driver</b>
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*
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* The XEmac driver is composed of several source files. Why so many? This
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* allows the user to build and link only those parts of the driver that are
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* necessary. Since the EMAC hardware can be configured in various ways (e.g.,
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* with or without DMA), the driver too can be built with varying features.
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* For the most part, this means that besides always linking in xemac.c, you
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* link in only the driver functionality you want. Some of the choices you have
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* are polled vs. interrupt, interrupt with FIFOs only vs. interrupt with DMA,
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* self-test diagnostics, and driver statistics. Note that currently the DMA code
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* must be linked in, even if you don't have DMA in the device.
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*
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* @note
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*
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* Xilinx drivers are typically composed of two components, one is the driver
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* and the other is the adapter. The driver is independent of OS and processor
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* and is intended to be highly portable. The adapter is OS-specific and
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* facilitates communication between the driver and an OS.
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* <br><br>
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* This driver is intended to be RTOS and processor independent. It works
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* with physical addresses only. Any needs for dynamic memory management,
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* threads or thread mutual exclusion, virtual memory, or cache control must
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* be satisfied by the layer above this driver.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a rpm 07/31/01 First release
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* 1.00b rpm 02/20/02 Repartitioned files and functions
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* 1.00b rpm 10/08/02 Replaced HasSgDma boolean with IpifDmaConfig enumerated
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* configuration parameter
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* 1.00c rpm 12/05/02 New version includes support for simple DMA and the delay
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* argument to SgSend
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* 1.00c rpm 02/03/03 The XST_DMA_SG_COUNT_EXCEEDED return code was removed
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* from SetPktThreshold in the internal DMA driver. Also
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* avoided compiler warnings by initializing Result in the
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* DMA interrupt service routines.
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* </pre>
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*
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******************************************************************************/
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#ifndef XEMAC_H /* prevent circular inclusions */
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#define XEMAC_H /* by using protection macros */
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/***************************** Include Files *********************************/
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#include <config.h>
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#include "xbasic_types.h"
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#include "xstatus.h"
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#include "xpacket_fifo_v1_00_b.h" /* Uses v1.00b of Packet Fifo */
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#include "xdma_channel.h"
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/************************** Constant Definitions *****************************/
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/*
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* Device information
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*/
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#define XEM_DEVICE_NAME "xemac"
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#define XEM_DEVICE_DESC "Xilinx Ethernet 10/100 MAC"
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/** @name Configuration options
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*
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* Device configuration options (see the XEmac_SetOptions() and
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* XEmac_GetOptions() for information on how to use these options)
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* @{
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*/
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/**
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* <pre>
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* XEM_BROADCAST_OPTION Broadcast addressing on or off (default is on)
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* XEM_UNICAST_OPTION Unicast addressing on or off (default is on)
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* XEM_PROMISC_OPTION Promiscuous addressing on or off (default is off)
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* XEM_FDUPLEX_OPTION Full duplex on or off (default is off)
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* XEM_POLLED_OPTION Polled mode on or off (default is off)
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* XEM_LOOPBACK_OPTION Internal loopback on or off (default is off)
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* XEM_FLOW_CONTROL_OPTION Interpret pause frames in full duplex mode
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* (default is off)
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* XEM_INSERT_PAD_OPTION Pad short frames on transmit (default is on)
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* XEM_INSERT_FCS_OPTION Insert FCS (CRC) on transmit (default is on)
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* XEM_INSERT_ADDR_OPTION Insert source address on transmit (default is on)
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* XEM_OVWRT_ADDR_OPTION Overwrite source address on transmit. This is
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* only used if source address insertion is on.
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* (default is on)
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* XEM_STRIP_PAD_FCS_OPTION Strip FCS and padding from received frames
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* (default is off)
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* </pre>
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*/
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#define XEM_UNICAST_OPTION 0x00000001UL
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#define XEM_BROADCAST_OPTION 0x00000002UL
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#define XEM_PROMISC_OPTION 0x00000004UL
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#define XEM_FDUPLEX_OPTION 0x00000008UL
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#define XEM_POLLED_OPTION 0x00000010UL
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#define XEM_LOOPBACK_OPTION 0x00000020UL
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#define XEM_FLOW_CONTROL_OPTION 0x00000080UL
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#define XEM_INSERT_PAD_OPTION 0x00000100UL
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#define XEM_INSERT_FCS_OPTION 0x00000200UL
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#define XEM_INSERT_ADDR_OPTION 0x00000400UL
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#define XEM_OVWRT_ADDR_OPTION 0x00000800UL
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#define XEM_STRIP_PAD_FCS_OPTION 0x00002000UL
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/*@}*/
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/*
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* Not supported yet:
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* XEM_MULTICAST_OPTION Multicast addressing on or off (default is off)
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*/
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/* NOT SUPPORTED YET... */
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#define XEM_MULTICAST_OPTION 0x00000040UL
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/*
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* Some default values for interrupt coalescing within the scatter-gather
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* DMA engine.
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*/
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#define XEM_SGDMA_DFT_THRESHOLD 1 /* Default pkt threshold */
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#define XEM_SGDMA_MAX_THRESHOLD 255 /* Maximum pkt theshold */
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#define XEM_SGDMA_DFT_WAITBOUND 5 /* Default pkt wait bound (msec) */
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#define XEM_SGDMA_MAX_WAITBOUND 1023 /* Maximum pkt wait bound (msec) */
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/*
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* Direction identifiers. These are used for setting values like packet
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* thresholds and wait bound for specific channels
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*/
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#define XEM_SEND 1
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#define XEM_RECV 2
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/*
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* Arguments to SgSend function to indicate whether to hold off starting
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* the scatter-gather engine.
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*/
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#define XEM_SGDMA_NODELAY 0 /* start SG DMA immediately */
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#define XEM_SGDMA_DELAY 1 /* do not start SG DMA */
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/*
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* Constants to determine the configuration of the hardware device. They are
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* used to allow the driver to verify it can operate with the hardware.
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*/
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#define XEM_CFG_NO_IPIF 0 /* Not supported by the driver */
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#define XEM_CFG_NO_DMA 1 /* No DMA */
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#define XEM_CFG_SIMPLE_DMA 2 /* Simple DMA */
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#define XEM_CFG_DMA_SG 3 /* DMA scatter gather */
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/*
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* The next few constants help upper layers determine the size of memory
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* pools used for Ethernet buffers and descriptor lists.
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*/
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#define XEM_MAC_ADDR_SIZE 6 /* six-byte MAC address */
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#define XEM_MTU 1500 /* max size of Ethernet frame */
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#define XEM_HDR_SIZE 14 /* size of Ethernet header */
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#define XEM_HDR_VLAN_SIZE 18 /* size of Ethernet header with VLAN */
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#define XEM_TRL_SIZE 4 /* size of Ethernet trailer (FCS) */
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#define XEM_MAX_FRAME_SIZE (XEM_MTU + XEM_HDR_SIZE + XEM_TRL_SIZE)
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#define XEM_MAX_VLAN_FRAME_SIZE (XEM_MTU + XEM_HDR_VLAN_SIZE + XEM_TRL_SIZE)
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/*
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* Define a default number of send and receive buffers
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*/
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#define XEM_MIN_RECV_BUFS 32 /* minimum # of recv buffers */
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#define XEM_DFT_RECV_BUFS 64 /* default # of recv buffers */
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#define XEM_MIN_SEND_BUFS 16 /* minimum # of send buffers */
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#define XEM_DFT_SEND_BUFS 32 /* default # of send buffers */
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#define XEM_MIN_BUFFERS (XEM_MIN_RECV_BUFS + XEM_MIN_SEND_BUFS)
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#define XEM_DFT_BUFFERS (XEM_DFT_RECV_BUFS + XEM_DFT_SEND_BUFS)
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/*
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* Define the number of send and receive buffer descriptors, used for
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* scatter-gather DMA
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*/
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#define XEM_MIN_RECV_DESC 16 /* minimum # of recv descriptors */
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#define XEM_DFT_RECV_DESC 32 /* default # of recv descriptors */
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#define XEM_MIN_SEND_DESC 8 /* minimum # of send descriptors */
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#define XEM_DFT_SEND_DESC 16 /* default # of send descriptors */
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/**************************** Type Definitions *******************************/
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/**
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* Ethernet statistics (see XEmac_GetStats() and XEmac_ClearStats())
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*/
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typedef struct {
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u32 XmitFrames; /**< Number of frames transmitted */
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u32 XmitBytes; /**< Number of bytes transmitted */
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u32 XmitLateCollisionErrors;
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/**< Number of transmission failures
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due to late collisions */
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u32 XmitExcessDeferral; /**< Number of transmission failures
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due o excess collision deferrals */
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u32 XmitOverrunErrors; /**< Number of transmit overrun errors */
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u32 XmitUnderrunErrors; /**< Number of transmit underrun errors */
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u32 RecvFrames; /**< Number of frames received */
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u32 RecvBytes; /**< Number of bytes received */
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u32 RecvFcsErrors; /**< Number of frames discarded due
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to FCS errors */
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u32 RecvAlignmentErrors; /**< Number of frames received with
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alignment errors */
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u32 RecvOverrunErrors; /**< Number of frames discarded due
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to overrun errors */
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u32 RecvUnderrunErrors; /**< Number of recv underrun errors */
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u32 RecvMissedFrameErrors;
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/**< Number of frames missed by MAC */
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u32 RecvCollisionErrors; /**< Number of frames discarded due
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to collisions */
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u32 RecvLengthFieldErrors;
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/**< Number of frames discarded with
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invalid length field */
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u32 RecvShortErrors; /**< Number of short frames discarded */
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u32 RecvLongErrors; /**< Number of long frames discarded */
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u32 DmaErrors; /**< Number of DMA errors since init */
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u32 FifoErrors; /**< Number of FIFO errors since init */
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u32 RecvInterrupts; /**< Number of receive interrupts */
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u32 XmitInterrupts; /**< Number of transmit interrupts */
|
|
u32 EmacInterrupts; /**< Number of MAC (device) interrupts */
|
|
u32 TotalIntrs; /**< Total interrupts */
|
|
} XEmac_Stats;
|
|
|
|
/**
|
|
* This typedef contains configuration information for a device.
|
|
*/
|
|
typedef struct {
|
|
u16 DeviceId; /**< Unique ID of device */
|
|
u32 BaseAddress; /**< Register base address */
|
|
u32 HasCounters; /**< Does device have counters? */
|
|
u8 IpIfDmaConfig; /**< IPIF/DMA hardware configuration */
|
|
u32 HasMii; /**< Does device support MII? */
|
|
|
|
} XEmac_Config;
|
|
|
|
/** @name Typedefs for callbacks
|
|
* Callback functions.
|
|
* @{
|
|
*/
|
|
/**
|
|
* Callback when data is sent or received with scatter-gather DMA.
|
|
*
|
|
* @param CallBackRef is a callback reference passed in by the upper layer
|
|
* when setting the callback functions, and passed back to the upper
|
|
* layer when the callback is invoked.
|
|
* @param BdPtr is a pointer to the first buffer descriptor in a list of
|
|
* buffer descriptors.
|
|
* @param NumBds is the number of buffer descriptors in the list pointed
|
|
* to by BdPtr.
|
|
*/
|
|
typedef void (*XEmac_SgHandler) (void *CallBackRef, XBufDescriptor * BdPtr,
|
|
u32 NumBds);
|
|
|
|
/**
|
|
* Callback when data is sent or received with direct FIFO communication or
|
|
* simple DMA. The user typically defines two callacks, one for send and one
|
|
* for receive.
|
|
*
|
|
* @param CallBackRef is a callback reference passed in by the upper layer
|
|
* when setting the callback functions, and passed back to the upper
|
|
* layer when the callback is invoked.
|
|
*/
|
|
typedef void (*XEmac_FifoHandler) (void *CallBackRef);
|
|
|
|
/**
|
|
* Callback when an asynchronous error occurs.
|
|
*
|
|
* @param CallBackRef is a callback reference passed in by the upper layer
|
|
* when setting the callback functions, and passed back to the upper
|
|
* layer when the callback is invoked.
|
|
* @param ErrorCode is a Xilinx error code defined in xstatus.h. Also see
|
|
* XEmac_SetErrorHandler() for a description of possible errors.
|
|
*/
|
|
typedef void (*XEmac_ErrorHandler) (void *CallBackRef, XStatus ErrorCode);
|
|
/*@}*/
|
|
|
|
/**
|
|
* The XEmac driver instance data. The user is required to allocate a
|
|
* variable of this type for every EMAC device in the system. A pointer
|
|
* to a variable of this type is then passed to the driver API functions.
|
|
*/
|
|
typedef struct {
|
|
u32 BaseAddress; /* Base address (of IPIF) */
|
|
u32 IsStarted; /* Device is currently started */
|
|
u32 IsReady; /* Device is initialized and ready */
|
|
u32 IsPolled; /* Device is in polled mode */
|
|
u8 IpIfDmaConfig; /* IPIF/DMA hardware configuration */
|
|
u32 HasMii; /* Does device support MII? */
|
|
u32 HasMulticastHash; /* Does device support multicast hash table? */
|
|
|
|
XEmac_Stats Stats;
|
|
XPacketFifoV100b RecvFifo; /* FIFO used to receive frames */
|
|
XPacketFifoV100b SendFifo; /* FIFO used to send frames */
|
|
|
|
/*
|
|
* Callbacks
|
|
*/
|
|
XEmac_FifoHandler FifoRecvHandler; /* for non-DMA/simple DMA interrupts */
|
|
void *FifoRecvRef;
|
|
XEmac_FifoHandler FifoSendHandler; /* for non-DMA/simple DMA interrupts */
|
|
void *FifoSendRef;
|
|
XEmac_ErrorHandler ErrorHandler; /* for asynchronous errors */
|
|
void *ErrorRef;
|
|
|
|
XDmaChannel RecvChannel; /* DMA receive channel driver */
|
|
XDmaChannel SendChannel; /* DMA send channel driver */
|
|
|
|
XEmac_SgHandler SgRecvHandler; /* callback for scatter-gather DMA */
|
|
void *SgRecvRef;
|
|
XEmac_SgHandler SgSendHandler; /* callback for scatter-gather DMA */
|
|
void *SgSendRef;
|
|
} XEmac;
|
|
|
|
/***************** Macros (Inline Functions) Definitions *********************/
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro determines if the device is currently configured for
|
|
* scatter-gather DMA.
|
|
*
|
|
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
|
|
*
|
|
* @return
|
|
*
|
|
* Boolean TRUE if the device is configured for scatter-gather DMA, or FALSE
|
|
* if it is not.
|
|
*
|
|
* @note
|
|
*
|
|
* Signature: u32 XEmac_mIsSgDma(XEmac *InstancePtr)
|
|
*
|
|
******************************************************************************/
|
|
#define XEmac_mIsSgDma(InstancePtr) \
|
|
((InstancePtr)->IpIfDmaConfig == XEM_CFG_DMA_SG)
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro determines if the device is currently configured for simple DMA.
|
|
*
|
|
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
|
|
*
|
|
* @return
|
|
*
|
|
* Boolean TRUE if the device is configured for simple DMA, or FALSE otherwise
|
|
*
|
|
* @note
|
|
*
|
|
* Signature: u32 XEmac_mIsSimpleDma(XEmac *InstancePtr)
|
|
*
|
|
******************************************************************************/
|
|
#define XEmac_mIsSimpleDma(InstancePtr) \
|
|
((InstancePtr)->IpIfDmaConfig == XEM_CFG_SIMPLE_DMA)
|
|
|
|
/*****************************************************************************/
|
|
/**
|
|
*
|
|
* This macro determines if the device is currently configured with DMA (either
|
|
* simple DMA or scatter-gather DMA)
|
|
*
|
|
* @param InstancePtr is a pointer to the XEmac instance to be worked on.
|
|
*
|
|
* @return
|
|
*
|
|
* Boolean TRUE if the device is configured with DMA, or FALSE otherwise
|
|
*
|
|
* @note
|
|
*
|
|
* Signature: u32 XEmac_mIsDma(XEmac *InstancePtr)
|
|
*
|
|
******************************************************************************/
|
|
#define XEmac_mIsDma(InstancePtr) \
|
|
(XEmac_mIsSimpleDma(InstancePtr) || XEmac_mIsSgDma(InstancePtr))
|
|
|
|
/************************** Function Prototypes ******************************/
|
|
|
|
/*
|
|
* Initialization functions in xemac.c
|
|
*/
|
|
XStatus XEmac_Initialize(XEmac * InstancePtr, u16 DeviceId);
|
|
XStatus XEmac_Start(XEmac * InstancePtr);
|
|
XStatus XEmac_Stop(XEmac * InstancePtr);
|
|
void XEmac_Reset(XEmac * InstancePtr);
|
|
XEmac_Config *XEmac_LookupConfig(u16 DeviceId);
|
|
|
|
/*
|
|
* Diagnostic functions in xemac_selftest.c
|
|
*/
|
|
XStatus XEmac_SelfTest(XEmac * InstancePtr);
|
|
|
|
/*
|
|
* Polled functions in xemac_polled.c
|
|
*/
|
|
XStatus XEmac_PollSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
|
|
XStatus XEmac_PollRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
|
|
|
|
/*
|
|
* Interrupts with scatter-gather DMA functions in xemac_intr_dma.c
|
|
*/
|
|
XStatus XEmac_SgSend(XEmac * InstancePtr, XBufDescriptor * BdPtr, int Delay);
|
|
XStatus XEmac_SgRecv(XEmac * InstancePtr, XBufDescriptor * BdPtr);
|
|
XStatus XEmac_SetPktThreshold(XEmac * InstancePtr, u32 Direction, u8 Threshold);
|
|
XStatus XEmac_GetPktThreshold(XEmac * InstancePtr, u32 Direction,
|
|
u8 * ThreshPtr);
|
|
XStatus XEmac_SetPktWaitBound(XEmac * InstancePtr, u32 Direction,
|
|
u32 TimerValue);
|
|
XStatus XEmac_GetPktWaitBound(XEmac * InstancePtr, u32 Direction,
|
|
u32 * WaitPtr);
|
|
XStatus XEmac_SetSgRecvSpace(XEmac * InstancePtr, u32 * MemoryPtr,
|
|
u32 ByteCount);
|
|
XStatus XEmac_SetSgSendSpace(XEmac * InstancePtr, u32 * MemoryPtr,
|
|
u32 ByteCount);
|
|
void XEmac_SetSgRecvHandler(XEmac * InstancePtr, void *CallBackRef,
|
|
XEmac_SgHandler FuncPtr);
|
|
void XEmac_SetSgSendHandler(XEmac * InstancePtr, void *CallBackRef,
|
|
XEmac_SgHandler FuncPtr);
|
|
|
|
void XEmac_IntrHandlerDma(void *InstancePtr); /* interrupt handler */
|
|
|
|
/*
|
|
* Interrupts with direct FIFO functions in xemac_intr_fifo.c. Also used
|
|
* for simple DMA.
|
|
*/
|
|
XStatus XEmac_FifoSend(XEmac * InstancePtr, u8 * BufPtr, u32 ByteCount);
|
|
XStatus XEmac_FifoRecv(XEmac * InstancePtr, u8 * BufPtr, u32 * ByteCountPtr);
|
|
void XEmac_SetFifoRecvHandler(XEmac * InstancePtr, void *CallBackRef,
|
|
XEmac_FifoHandler FuncPtr);
|
|
void XEmac_SetFifoSendHandler(XEmac * InstancePtr, void *CallBackRef,
|
|
XEmac_FifoHandler FuncPtr);
|
|
|
|
void XEmac_IntrHandlerFifo(void *InstancePtr); /* interrupt handler */
|
|
|
|
/*
|
|
* General interrupt-related functions in xemac_intr.c
|
|
*/
|
|
void XEmac_SetErrorHandler(XEmac * InstancePtr, void *CallBackRef,
|
|
XEmac_ErrorHandler FuncPtr);
|
|
|
|
/*
|
|
* MAC configuration in xemac_options.c
|
|
*/
|
|
XStatus XEmac_SetOptions(XEmac * InstancePtr, u32 OptionFlag);
|
|
u32 XEmac_GetOptions(XEmac * InstancePtr);
|
|
XStatus XEmac_SetMacAddress(XEmac * InstancePtr, u8 * AddressPtr);
|
|
void XEmac_GetMacAddress(XEmac * InstancePtr, u8 * BufferPtr);
|
|
XStatus XEmac_SetInterframeGap(XEmac * InstancePtr, u8 Part1, u8 Part2);
|
|
void XEmac_GetInterframeGap(XEmac * InstancePtr, u8 * Part1Ptr, u8 * Part2Ptr);
|
|
|
|
/*
|
|
* Multicast functions in xemac_multicast.c (not supported by EMAC yet)
|
|
*/
|
|
XStatus XEmac_MulticastAdd(XEmac * InstancePtr, u8 * AddressPtr);
|
|
XStatus XEmac_MulticastClear(XEmac * InstancePtr);
|
|
|
|
/*
|
|
* PHY configuration in xemac_phy.c
|
|
*/
|
|
XStatus XEmac_PhyRead(XEmac * InstancePtr, u32 PhyAddress,
|
|
u32 RegisterNum, u16 * PhyDataPtr);
|
|
XStatus XEmac_PhyWrite(XEmac * InstancePtr, u32 PhyAddress,
|
|
u32 RegisterNum, u16 PhyData);
|
|
|
|
/*
|
|
* Statistics in xemac_stats.c
|
|
*/
|
|
void XEmac_GetStats(XEmac * InstancePtr, XEmac_Stats * StatsPtr);
|
|
void XEmac_ClearStats(XEmac * InstancePtr);
|
|
|
|
#endif /* end of protection macro */
|