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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
220 lines
4.7 KiB
C
220 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <init.h>
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#include <time.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/armv8/mmu.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <zynqmp_firmware.h>
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#include <asm/cache.h>
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#define ZYNQ_SILICON_VER_MASK 0xF000
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#define ZYNQ_SILICON_VER_SHIFT 12
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Number of filled static entries and also the first empty
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* slot in zynqmp_mem_map.
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*/
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#define ZYNQMP_MEM_MAP_USED 4
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#if !defined(CONFIG_ZYNQMP_NO_DDR)
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#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
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#else
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#define DRAM_BANKS 0
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#endif
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#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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#define TCM_MAP 1
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#else
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#define TCM_MAP 0
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#endif
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/* +1 is end of list which needs to be empty */
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#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
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static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
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{
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x70000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0xf8000000UL,
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.phys = 0xf8000000UL,
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.size = 0x07e00000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x400000000UL,
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.phys = 0x400000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x1000000000UL,
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.phys = 0x1000000000UL,
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.size = 0xf000000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}
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};
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void mem_map_fill(void)
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{
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int banks = ZYNQMP_MEM_MAP_USED;
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#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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zynqmp_mem_map[banks].virt = 0xffe00000UL;
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zynqmp_mem_map[banks].phys = 0xffe00000UL;
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zynqmp_mem_map[banks].size = 0x00200000UL;
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zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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banks = banks + 1;
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#endif
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#if !defined(CONFIG_ZYNQMP_NO_DDR)
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for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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/* Zero size means no more DDR that's this is end */
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if (!gd->bd->bi_dram[i].size)
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break;
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zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
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zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
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zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
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zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE;
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banks = banks + 1;
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}
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#endif
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}
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struct mm_region *mem_map = zynqmp_mem_map;
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u64 get_page_table_size(void)
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{
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return 0x14000;
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}
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#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
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void tcm_init(u8 mode)
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{
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puts("WARNING: Initializing TCM overwrites TCM content\n");
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initialize_tcm(mode);
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memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
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}
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#endif
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#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
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int arm_reserve_mmu(void)
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{
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tcm_init(TCM_LOCK);
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gd->arch.tlb_size = PGTABLE_SIZE;
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gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
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return 0;
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}
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#endif
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static unsigned int zynqmp_get_silicon_version_secure(void)
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{
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u32 ver;
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ver = readl(&csu_base->version);
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ver &= ZYNQMP_SILICON_VER_MASK;
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ver >>= ZYNQMP_SILICON_VER_SHIFT;
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return ver;
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}
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unsigned int zynqmp_get_silicon_version(void)
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{
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if (current_el() == 3)
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return zynqmp_get_silicon_version_secure();
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gd->cpu_clk = get_tbclk();
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switch (gd->cpu_clk) {
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case 50000000:
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return ZYNQMP_CSU_VERSION_QEMU;
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}
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return ZYNQMP_CSU_VERSION_SILICON;
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}
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static int zynqmp_mmio_rawwrite(const u32 address,
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const u32 mask,
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const u32 value)
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{
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u32 data;
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u32 value_local = value;
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int ret;
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ret = zynqmp_mmio_read(address, &data);
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if (ret)
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return ret;
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data &= ~mask;
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value_local &= mask;
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value_local |= data;
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writel(value_local, (ulong)address);
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return 0;
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}
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static int zynqmp_mmio_rawread(const u32 address, u32 *value)
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{
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*value = readl((ulong)address);
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return 0;
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}
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int zynqmp_mmio_write(const u32 address,
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const u32 mask,
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const u32 value)
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{
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if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
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return zynqmp_mmio_rawwrite(address, mask, value);
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#if defined(CONFIG_ZYNQMP_FIRMWARE)
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else
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return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
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value, 0, NULL);
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#endif
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return -EINVAL;
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}
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int zynqmp_mmio_read(const u32 address, u32 *value)
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{
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u32 ret = -EINVAL;
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if (!value)
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return ret;
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if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
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ret = zynqmp_mmio_rawread(address, value);
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}
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#if defined(CONFIG_ZYNQMP_FIRMWARE)
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else {
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
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0, ret_payload);
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*value = ret_payload[1];
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}
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#endif
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return ret;
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}
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