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912cc40f76
u-boot-brain/arch/arm/cpu/armv8/fsl-lsch3
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Bhupesh Sharma 912cc40f76 armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes 
This patch adds the fdt-fixup logic for the clock frequency of the
NS16550A related device tree nodes.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-02-24 13:08:53 -08:00
..
cpu.c armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack 2015-02-24 13:08:46 -08:00
cpu.h armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
fdt.c armv8/fsl-lsch3: Add fdt-fixup for clock frequency of the DUART nodes 2015-02-24 13:08:53 -08:00
lowlevel.S armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack 2015-02-24 13:08:46 -08:00
Makefile armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page 2014-09-25 08:36:19 -07:00
mp.c ARMv8/fsl-lsch3: Patch cpu node properties in DT for online cores 2015-02-24 13:08:28 -08:00
mp.h ARMv8/fsl-lsch3: Patch cpu node properties in DT for online cores 2015-02-24 13:08:28 -08:00
README ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support 2014-07-04 19:48:41 +02:00
speed.c ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00
speed.h ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC 2014-07-03 08:40:51 +02:00

README 

#
# Copyright 2014 Freescale Semiconductor
#
# SPDX-License-Identifier:      GPL-2.0+
#

Freescale LayerScape with Chassis Generation 3

This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
for example LS2085A.