mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
3a8ee3df83
This uclass is intended to provide a way to obtain information about a U-Boot board. But the concept of a U-Boot 'board' is the whole system, not just one circuit board, meaning that 'board' is something of a misnomer for this uclass. In addition, the name 'board' is a bit overused in U-Boot and we want to use the same uclass to provide SMBIOS information. The obvious name is 'system' but that is so vague as to be meaningless. Use 'sysinfo' instead, since this uclass is aimed at providing information on the system. Rename everything accordingly. Note: Due to the patch delta caused by the symbol renames, this patch shows some renamed files as being deleted in one place and created in another. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
213 lines
5.1 KiB
Plaintext
213 lines
5.1 KiB
Plaintext
CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0xFE000000
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CONFIG_SYS_MALLOC_F_LEN=0x600
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_DM_GPIO=y
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CONFIG_IDENT_STRING=" gazerbeam 0.01"
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CONFIG_SYS_CLK_FREQ=33333333
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CONFIG_DEFAULT_DEVICE_TREE="gazerbeam"
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CONFIG_MPC83xx=y
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CONFIG_TARGET_GAZERBEAM=y
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CONFIG_SYSTEM_PLL_VCO_DIV_2=y
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CONFIG_SYSTEM_PLL_FACTOR_4_1=y
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CONFIG_CORE_PLL_RATIO_3_1=y
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CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
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CONFIG_TSEC1_MODE_RGMII=y
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CONFIG_TSEC2_MODE_RGMII=y
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CONFIG_BAT0=y
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CONFIG_BAT0_NAME="SDRAM"
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CONFIG_BAT0_BASE=0x00000000
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CONFIG_BAT0_LENGTH_128_MBYTES=y
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CONFIG_BAT0_ACCESS_RW=y
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CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
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CONFIG_BAT0_USER_MODE_VALID=y
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CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT1=y
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CONFIG_BAT1_NAME="IMMR"
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CONFIG_BAT1_BASE=0xE0000000
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CONFIG_BAT1_LENGTH_8_MBYTES=y
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CONFIG_BAT1_ACCESS_RW=y
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CONFIG_BAT1_ICACHE_INHIBITED=y
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CONFIG_BAT1_ICACHE_GUARDED=y
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CONFIG_BAT1_DCACHE_INHIBITED=y
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CONFIG_BAT1_DCACHE_GUARDED=y
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CONFIG_BAT1_USER_MODE_VALID=y
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CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT2=y
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CONFIG_BAT2_NAME="FLASH"
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CONFIG_BAT2_BASE=0xFE000000
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CONFIG_BAT2_LENGTH_8_MBYTES=y
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CONFIG_BAT2_ACCESS_RW=y
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CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
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CONFIG_BAT2_DCACHE_INHIBITED=y
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CONFIG_BAT2_DCACHE_GUARDED=y
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CONFIG_BAT2_USER_MODE_VALID=y
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CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
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CONFIG_BAT3=y
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CONFIG_BAT3_NAME="INIT_RAM"
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CONFIG_BAT3_BASE=0xE6000000
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CONFIG_BAT3_ACCESS_RW=y
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CONFIG_BAT3_USER_MODE_VALID=y
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CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
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CONFIG_LBLAW0=y
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CONFIG_LBLAW0_BASE=0xFE000000
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CONFIG_LBLAW0_NAME="FLASH"
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CONFIG_LBLAW0_LENGTH_8_MBYTES=y
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CONFIG_LBLAW1=y
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CONFIG_LBLAW1_BASE=0xE0600000
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CONFIG_LBLAW1_NAME="FPGA0"
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CONFIG_LBLAW1_LENGTH_1_MBYTES=y
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CONFIG_LBLAW2=y
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CONFIG_LBLAW2_BASE=0xE0700000
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CONFIG_LBLAW2_NAME="FPGA1"
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CONFIG_LBLAW2_LENGTH_1_MBYTES=y
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CONFIG_ELBC_BR0_OR0=y
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CONFIG_BR0_OR0_NAME="FLASH"
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CONFIG_BR0_OR0_BASE=0xFE000000
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CONFIG_BR0_PORTSIZE_16BIT=y
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CONFIG_OR0_AM_8_MBYTES=y
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CONFIG_OR0_SCY_15=y
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CONFIG_OR0_CSNT_EARLIER=y
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CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
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CONFIG_OR0_XACS_EXTENDED=y
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CONFIG_OR0_TRLX_RELAXED=y
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CONFIG_OR0_EHTR_8_CYCLE=y
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CONFIG_ELBC_BR1_OR1=y
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CONFIG_BR1_OR1_NAME="FPGA0"
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CONFIG_BR1_OR1_BASE=0xE0600000
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CONFIG_BR1_PORTSIZE_16BIT=y
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CONFIG_OR1_AM_1_MBYTES=y
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CONFIG_OR1_SCY_5=y
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CONFIG_OR1_CSNT_EARLIER=y
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CONFIG_ELBC_BR2_OR2=y
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CONFIG_BR2_OR2_NAME="FPGA1"
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CONFIG_BR2_OR2_BASE=0xE0700000
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CONFIG_BR2_PORTSIZE_16BIT=y
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CONFIG_OR2_AM_1_MBYTES=y
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CONFIG_OR2_SCY_5=y
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CONFIG_OR2_CSNT_EARLIER=y
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CONFIG_HID0_FINAL_EMCP=y
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CONFIG_HID0_FINAL_DPM=y
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CONFIG_HID0_FINAL_ICE=y
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CONFIG_HID2_HBE=y
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CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y
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CONFIG_SICR_GPIO_A_TSEC2=y
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CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y
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CONFIG_SICR_IEEE1588_A_GPIO=y
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CONFIG_SICR_GTM_GPIO=y
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CONFIG_SICR_ETSEC2_GPIO=y
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CONFIG_SICR_GPIOSEL_IEEE1588=y
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CONFIG_SICR_TMSOBI1_2_5_V=y
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CONFIG_SICR_TMSOBI2_2_5_V=y
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CONFIG_ACR_PIPE_DEP_4=y
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CONFIG_ACR_RPTCNT_4=y
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CONFIG_SPCR_TSECEP_3=y
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CONFIG_LCRR_DBYP_PLL_BYPASSED=y
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CONFIG_LCRR_CLKDIV_2=y
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CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y
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CONFIG_CMD_IOLOOP=y
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CONFIG_FIT=y
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CONFIG_FIT_SIGNATURE=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_BOOTDELAY=5
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_STOP_STR=" "
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_DISPLAY_CPUINFO=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_BOARD_EARLY_INIT_R=y
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CONFIG_LAST_STAGE_INIT=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_CPU=y
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CONFIG_CMD_BINOP=y
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_ALT_MEMTEST=y
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CONFIG_SYS_MEMTEST_START=0x00001000
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CONFIG_SYS_MEMTEST_END=0x07e00000
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_AXI=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_HASH=y
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CONFIG_CMD_TPM=y
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CONFIG_CMD_EXT2=y
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CONFIG_DOS_PARTITION=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
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CONFIG_ENV_ADDR=0xFE080000
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CONFIG_ENV_ADDR_REDUND=0xFE090000
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CONFIG_DM=y
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CONFIG_REGMAP=y
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CONFIG_AXI=y
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CONFIG_IHS_AXI=y
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CONFIG_CLK=y
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CONFIG_ICS8N3QV01=y
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CONFIG_CPU=y
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CONFIG_CPU_MPC83XX=y
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CONFIG_DM_PCA953X=y
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CONFIG_MPC8XXX_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_I2C_IHS=y
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CONFIG_MISC=y
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CONFIG_GDSYS_RXAUI_CTRL=y
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CONFIG_GDSYS_IOEP=y
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CONFIG_MPC83XX_SERDES=y
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CONFIG_GDSYS_SOC=y
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CONFIG_IHS_FPGA=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_PHYLIB_10G=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_BROADCOM=y
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CONFIG_PHY_DAVICOM=y
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CONFIG_PHY_LXT=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_NATSEMI=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_SMSC=y
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CONFIG_PHY_TERANETICS=y
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CONFIG_PHY_VITESSE=y
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CONFIG_DM_ETH=y
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CONFIG_TSEC_ENET=y
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# CONFIG_PCI is not set
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CONFIG_RAM=y
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CONFIG_MPC83XX_SDRAM=y
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CONFIG_DM_RESET=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYSINFO=y
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CONFIG_SYSINFO_GAZERBEAM=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_MPC83XX=y
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CONFIG_TIMER=y
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CONFIG_MPC83XX_TIMER=y
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CONFIG_TPM_ATMEL_TWI=y
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CONFIG_TPM_AUTH_SESSIONS=y
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# CONFIG_TPM_V2 is not set
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CONFIG_DM_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_LOGICORE_DP_TX=y
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CONFIG_OSD=y
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CONFIG_IHS_VIDEO_OUT=y
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CONFIG_TPM=y
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