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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
161 lines
4.3 KiB
C
161 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013-2015 Arcturus Networks, Inc.
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* http://www.arcturusnetworks.com/products/ucp1020/
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* based on board/freescale/p1_p2_rdb_pc/spl.c
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* original copyright follows:
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
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/*
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* Micron MT41J128M16HA-15E
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* */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 536870912u,
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.capacity = 536870912u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 14,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 2,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1650,
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.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
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.taa_ps = 14050,
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.twr_ps = 15000,
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.trcd_ps = 13500,
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.trrd_ps = 75000,
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.trp_ps = 13500,
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.tras_ps = 40000,
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.trc_ps = 49500,
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.trfc_ps = 160000,
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.twtr_ps = 75000,
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.trtp_ps = 75000,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 30000,
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};
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#else
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#error Missing raw timing data for this board
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#endif
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR on board";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#endif /* CONFIG_SYS_DDR_RAW_TIMING */
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#ifdef CONFIG_SYS_DDR_CS0_BNDS
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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sys_info_t sysinfo;
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char buf[32];
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size_t ddr_size;
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fsl_ddr_cfg_regs_t ddr_cfg_regs = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
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#endif
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
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.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freq_ddrbus));
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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};
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return ddr_size;
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}
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#endif
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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int i;
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popts->clk_adjust = 6;
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popts->cpo_override = 0x1f;
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popts->write_data_delay = 2;
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popts->half_strength_driver_enable = 1;
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/* Write leveling override */
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popts->wrlvl_en = 1;
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x8;
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popts->trwt_override = 1;
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popts->trwt = 0;
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if (pdimm->primary_sdram_width == 64)
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popts->data_bus_width = 0;
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else if (pdimm->primary_sdram_width == 32)
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popts->data_bus_width = 1;
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else
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printf("Error in DDR bus width configuration!\n");
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
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popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
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}
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}
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