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910df4d07e
Add PFC pincontrol driver for the Renesas RCar Gen3 R8A7795 and R8A7796 SoCs. This driver uses the PFC pin tables from Linux, thus letting us share the occassional fixes to those tables. This driver also has a DT support, so the pinmux is configured from DT instead of the ad-hoc setup in board file. This driver is meant to replace the pinmux part of SH_GPIO_PFC driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
576 lines
18 KiB
C
576 lines
18 KiB
C
/*
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* SuperH Pin Function Controller Support
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*
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* Copyright (c) 2008 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __SH_PFC_H
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#define __SH_PFC_H
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#include <linux/stringify.h>
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enum {
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PINMUX_TYPE_NONE,
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PINMUX_TYPE_FUNCTION,
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PINMUX_TYPE_GPIO,
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PINMUX_TYPE_OUTPUT,
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PINMUX_TYPE_INPUT,
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};
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#define SH_PFC_PIN_CFG_INPUT (1 << 0)
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#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
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#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
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#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
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#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
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#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
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#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
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struct sh_pfc_pin {
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u16 pin;
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u16 enum_id;
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const char *name;
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unsigned int configs;
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};
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#define SH_PFC_PIN_GROUP(n) \
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{ \
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.name = #n, \
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.pins = n##_pins, \
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.mux = n##_mux, \
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.nr_pins = ARRAY_SIZE(n##_pins), \
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}
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struct sh_pfc_pin_group {
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const char *name;
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const unsigned int *pins;
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const unsigned int *mux;
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unsigned int nr_pins;
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};
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/*
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* Using union vin_data saves memory occupied by the VIN data pins.
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* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
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* in this case.
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*/
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#define VIN_DATA_PIN_GROUP(n, s) \
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{ \
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.name = #n#s, \
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.pins = n##_pins.data##s, \
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.mux = n##_mux.data##s, \
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.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
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}
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union vin_data {
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unsigned int data24[24];
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unsigned int data20[20];
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unsigned int data16[16];
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unsigned int data12[12];
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unsigned int data10[10];
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unsigned int data8[8];
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unsigned int data4[4];
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};
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#define SH_PFC_FUNCTION(n) \
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{ \
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.name = #n, \
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.groups = n##_groups, \
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.nr_groups = ARRAY_SIZE(n##_groups), \
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}
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struct sh_pfc_function {
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const char *name;
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const char * const *groups;
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unsigned int nr_groups;
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};
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struct pinmux_func {
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u16 enum_id;
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const char *name;
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};
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struct pinmux_cfg_reg {
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u32 reg;
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u8 reg_width, field_width;
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const u16 *enum_ids;
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const u8 *var_field_width;
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};
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/*
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* Describe a config register consisting of several fields of the same width
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - f_width: Width of the fixed-width register fields (in bits)
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* This macro must be followed by initialization data: For each register field
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* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
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* one for each possible combination of the register field bit values.
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*/
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#define PINMUX_CFG_REG(name, r, r_width, f_width) \
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.reg = r, .reg_width = r_width, .field_width = f_width, \
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.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
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/*
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* Describe a config register consisting of several fields of different widths
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
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* From left to right (i.e. MSB to LSB)
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* This macro must be followed by initialization data: For each register field
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* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
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* one for each possible combination of the register field bit values.
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*/
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#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
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.reg = r, .reg_width = r_width, \
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.var_field_width = (const u8 [r_width]) \
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{ var_fw0, var_fwn, 0 }, \
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.enum_ids = (const u16 [])
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struct pinmux_drive_reg_field {
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u16 pin;
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u8 offset;
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u8 size;
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};
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struct pinmux_drive_reg {
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u32 reg;
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const struct pinmux_drive_reg_field fields[8];
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};
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#define PINMUX_DRIVE_REG(name, r) \
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.reg = r, \
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.fields =
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struct pinmux_data_reg {
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u32 reg;
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u8 reg_width;
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const u16 *enum_ids;
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};
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/*
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* Describe a data register
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* - name: Register name (unused, for documentation purposes only)
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* - r: Physical register address
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* - r_width: Width of the register (in bits)
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* This macro must be followed by initialization data: For each register bit
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* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
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*/
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#define PINMUX_DATA_REG(name, r, r_width) \
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.reg = r, .reg_width = r_width, \
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.enum_ids = (const u16 [r_width]) \
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struct pinmux_irq {
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const short *gpios;
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};
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/*
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* Describe the mapping from GPIOs to a single IRQ
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* - ids...: List of GPIOs that are mapped to the same IRQ
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*/
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#define PINMUX_IRQ(ids...) \
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{ .gpios = (const short []) { ids, -1 } }
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struct pinmux_range {
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u16 begin;
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u16 end;
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u16 force;
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};
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struct sh_pfc_bias_info {
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u16 pin;
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u16 reg : 11;
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u16 bit : 5;
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};
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struct sh_pfc_pin_range;
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struct sh_pfc {
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struct device *dev;
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const struct sh_pfc_soc_info *info;
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void *regs;
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struct sh_pfc_pin_range *ranges;
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unsigned int nr_ranges;
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unsigned int nr_gpio_pins;
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struct sh_pfc_chip *gpio;
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};
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struct sh_pfc_soc_operations {
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int (*init)(struct sh_pfc *pfc);
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unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
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void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
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unsigned int bias);
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int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
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};
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struct sh_pfc_soc_info {
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const char *name;
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const struct sh_pfc_soc_operations *ops;
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struct pinmux_range input;
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struct pinmux_range output;
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struct pinmux_range function;
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const struct sh_pfc_pin *pins;
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unsigned int nr_pins;
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const struct sh_pfc_pin_group *groups;
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unsigned int nr_groups;
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const struct sh_pfc_function *functions;
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unsigned int nr_functions;
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const struct pinmux_cfg_reg *cfg_regs;
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const struct pinmux_drive_reg *drive_regs;
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const struct pinmux_data_reg *data_regs;
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const u16 *pinmux_data;
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unsigned int pinmux_data_size;
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const struct pinmux_irq *gpio_irq;
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unsigned int gpio_irq_size;
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u32 unlock_reg;
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};
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u32 sh_pfc_read_reg(struct sh_pfc *pfc, u32 reg, unsigned int width);
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void sh_pfc_write_reg(struct sh_pfc *pfc, u32 reg, unsigned int width, u32 data);
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const struct sh_pfc_bias_info *
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sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info *info,
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unsigned int num, unsigned int pin);
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extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
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extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
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/* -----------------------------------------------------------------------------
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* Helper macros to create pin and port lists
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*/
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/*
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* sh_pfc_soc_info pinmux_data array macros
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*/
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/*
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* Describe generic pinmux data
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* - data_or_mark: *_DATA or *_MARK enum ID
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* - ids...: List of enum IDs to associate with data_or_mark
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*/
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#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
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/*
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* Describe a pinmux configuration without GPIO function that needs
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* configuration in a Peripheral Function Select Register (IPSR)
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* - ipsr: IPSR field (unused, for documentation purposes only)
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* - fn: Function name, referring to a field in the IPSR
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*/
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#define PINMUX_IPSR_NOGP(ipsr, fn) \
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PINMUX_DATA(fn##_MARK, FN_##fn)
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/*
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* Describe a pinmux configuration with GPIO function that needs configuration
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* in both a Peripheral Function Select Register (IPSR) and in a
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* GPIO/Peripheral Function Select Register (GPSR)
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* - ipsr: IPSR field
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* - fn: Function name, also referring to the IPSR field
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*/
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#define PINMUX_IPSR_GPSR(ipsr, fn) \
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PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
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/*
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* Describe a pinmux configuration without GPIO function that needs
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* configuration in a Peripheral Function Select Register (IPSR), and where the
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* pinmux function has a representation in a Module Select Register (MOD_SEL).
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* - ipsr: IPSR field (unused, for documentation purposes only)
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* - fn: Function name, also referring to the IPSR field
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* - msel: Module selector
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*/
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#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
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PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
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/*
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* Describe a pinmux configuration with GPIO function where the pinmux function
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* has no representation in a Peripheral Function Select Register (IPSR), but
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* instead solely depends on a group selection.
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* - gpsr: GPSR field
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* - fn: Function name, also referring to the GPSR field
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* - gsel: Group selector
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*/
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#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
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PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
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/*
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* Describe a pinmux configuration with GPIO function that needs configuration
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* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
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* Function Select Register (GPSR), and where the pinmux function has a
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* representation in a Module Select Register (MOD_SEL).
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* - ipsr: IPSR field
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* - fn: Function name, also referring to the IPSR field
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* - msel: Module selector
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*/
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#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
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PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
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/*
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* Describe a pinmux configuration for a single-function pin with GPIO
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* capability.
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* - fn: Function name
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*/
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#define PINMUX_SINGLE(fn) \
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PINMUX_DATA(fn##_MARK, FN_##fn)
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/*
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* GP port style (32 ports banks)
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*/
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#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
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fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
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#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
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#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
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PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
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#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
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#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
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PORT_GP_CFG_4(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
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#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
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#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
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PORT_GP_CFG_8(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
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#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
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#define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
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PORT_GP_CFG_9(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
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#define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
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#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
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PORT_GP_CFG_10(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
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#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
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#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
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PORT_GP_CFG_12(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
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#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
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#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
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PORT_GP_CFG_14(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
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#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
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#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
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PORT_GP_CFG_15(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
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#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
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#define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
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PORT_GP_CFG_16(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
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#define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
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#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
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PORT_GP_CFG_17(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
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#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
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#define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
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PORT_GP_CFG_18(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
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#define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
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#define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
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PORT_GP_CFG_20(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
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#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
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#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
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PORT_GP_CFG_21(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
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#define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
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#define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
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PORT_GP_CFG_23(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
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#define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
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#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
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PORT_GP_CFG_24(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
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#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
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#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
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PORT_GP_CFG_26(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
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#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
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#define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
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PORT_GP_CFG_28(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
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#define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
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#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
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PORT_GP_CFG_29(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
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#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
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#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
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PORT_GP_CFG_30(bank, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
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PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
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#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
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#define PORT_GP_32_REV(bank, fn, sfx) \
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PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
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PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
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PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
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PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
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PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
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PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
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PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
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PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
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PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
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PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
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PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
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PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
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PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
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PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
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PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
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PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
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/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
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#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
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#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
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/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
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#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
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{ \
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.pin = (bank * 32) + _pin, \
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.name = __stringify(_name), \
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.enum_id = _name##_DATA, \
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.configs = cfg, \
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}
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#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
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/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
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#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
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#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
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/*
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* PORT style (linear pin space)
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*/
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#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
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#define PORT_10(pn, fn, pfx, sfx) \
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PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
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PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
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PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
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PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
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PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
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#define PORT_90(pn, fn, pfx, sfx) \
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PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
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PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
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PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
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PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
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PORT_10(pn+90, fn, pfx##9, sfx)
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/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
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#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
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#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
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/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
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#define PINMUX_GPIO(_pin) \
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[GPIO_##_pin] = { \
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.pin = (u16)-1, \
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.name = __stringify(GPIO_##_pin), \
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.enum_id = _pin##_DATA, \
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}
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/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
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#define SH_PFC_PIN_CFG(_pin, cfgs) \
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{ \
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.pin = _pin, \
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.name = __stringify(PORT##_pin), \
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.enum_id = PORT##_pin##_DATA, \
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.configs = cfgs, \
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}
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/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
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#define SH_PFC_PIN_NAMED(row, col, _name) \
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{ \
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.pin = PIN_NUMBER(row, col), \
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.name = __stringify(PIN_##_name), \
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.configs = SH_PFC_PIN_CFG_NO_GPIO, \
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}
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/* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
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#define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
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{ \
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.pin = PIN_NUMBER(row, col), \
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.name = __stringify(PIN_##_name), \
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.configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
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}
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/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
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* PORT_name_OUT, PORT_name_IN marks
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*/
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#define _PORT_DATA(pn, pfx, sfx) \
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PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
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PORT##pfx##_OUT, PORT##pfx##_IN)
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#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
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/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
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#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
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[gpio - (base)] = { \
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.name = __stringify(gpio), \
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.enum_id = data_or_mark, \
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}
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#define GPIO_FN(str) \
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PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
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/*
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* PORTnCR helper macro for SH-Mobile/R-Mobile
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*/
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#define PORTCR(nr, reg) \
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{ \
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PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
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/* PULMD[1:0], handled by .set_bias() */ \
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0, 0, 0, 0, \
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/* IE and OE */ \
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0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
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/* SEC, not supported */ \
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0, 0, \
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/* PTMD[2:0] */ \
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PORT##nr##_FN0, PORT##nr##_FN1, \
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PORT##nr##_FN2, PORT##nr##_FN3, \
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PORT##nr##_FN4, PORT##nr##_FN5, \
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PORT##nr##_FN6, PORT##nr##_FN7 \
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} \
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}
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/*
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* GPIO number helper macro for R-Car
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*/
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#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
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#endif /* __SH_PFC_H */
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