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https://github.com/brain-hackers/u-boot-brain
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AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
70 lines
1.8 KiB
Plaintext
70 lines
1.8 KiB
Plaintext
if RAM || SPL_RAM
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config ASPEED_DDR4_DUALX8
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bool "Enable Dual X8 DDR4 die"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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default n
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help
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Say Y if dual X8 DDR4 die is used on the board. The aspeed ddr sdram
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controller needs to know if the memory chip mounted on the board is dual
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x8 die or not. Or it may get the wrong size of the memory space.
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if ASPEED_AST2600
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choice
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prompt "DDR4 target date rate"
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default ASPEED_DDR4_1600
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config ASPEED_DDR4_400
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bool "DDR4 targets at 400Mbps"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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help
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select DDR4 target data rate at 400M
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config ASPEED_DDR4_800
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bool "DDR4 targets at 800Mbps"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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help
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select DDR4 target data rate at 800M
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config ASPEED_DDR4_1333
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bool "DDR4 targets at 1333Mbps"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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help
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select DDR4 target data rate at 1333M
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config ASPEED_DDR4_1600
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bool "DDR4 targets at 1600Mbps"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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help
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select DDR4 target data rate at 1600M
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endchoice
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config ASPEED_BYPASS_SELFTEST
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bool "bypass self test during DRAM initialization"
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default n
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help
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Say Y here to bypass DRAM self test to speed up the boot time
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config ASPEED_ECC
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bool "aspeed SDRAM error correcting code"
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depends on DM && OF_CONTROL && ARCH_ASPEED
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default n
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help
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enable SDRAM ECC function
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if ASPEED_ECC
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config ASPEED_ECC_SIZE
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int "ECC size: 0=driver auto-caluated"
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depends on ASPEED_ECC
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default 0
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help
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SDRAM size with the error correcting code enabled. The unit is
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in Megabytes. Noted that only the 8/9 of the configured size
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can be used by the system. The remaining 1/9 will be used by
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the ECC engine. If the size is set to 0, the sdram driver will
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calculate the SDRAM size and set the whole range be ECC enabled.
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endif # end of ASPEED_ECC
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endif # end of ASPEED_AST2600
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endif # end of RAM || SPL_RAM
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