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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
![Vignesh R](/assets/img/avatar_default.png)
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
377 lines
9.4 KiB
C
377 lines
9.4 KiB
C
/*
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* TI QSPI driver
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/omap.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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#include <asm/omap_common.h>
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#include <asm/ti-common/ti-edma3.h>
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/* ti qpsi register bit masks */
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#define QSPI_TIMEOUT 2000000
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#define QSPI_FCLK 192000000
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/* clock control */
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#define QSPI_CLK_EN BIT(31)
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#define QSPI_CLK_DIV_MAX 0xffff
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/* command */
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#define QSPI_EN_CS(n) (n << 28)
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#define QSPI_WLEN(n) ((n-1) << 19)
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#define QSPI_3_PIN BIT(18)
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#define QSPI_RD_SNGL BIT(16)
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#define QSPI_WR_SNGL (2 << 16)
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#define QSPI_INVAL (4 << 16)
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#define QSPI_RD_QUAD (7 << 16)
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/* device control */
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#define QSPI_DD(m, n) (m << (3 + n*8))
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#define QSPI_CKPHA(n) (1 << (2 + n*8))
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#define QSPI_CSPOL(n) (1 << (1 + n*8))
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#define QSPI_CKPOL(n) (1 << (n*8))
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/* status */
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#define QSPI_WC BIT(1)
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#define QSPI_BUSY BIT(0)
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#define QSPI_WC_BUSY (QSPI_WC | QSPI_BUSY)
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#define QSPI_XFER_DONE QSPI_WC
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#define MM_SWITCH 0x01
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#define MEM_CS 0x100
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#define MEM_CS_UNSELECT 0xfffff0ff
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#define MMAP_START_ADDR_DRA 0x5c000000
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#define MMAP_START_ADDR_AM43x 0x30000000
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#define CORE_CTRL_IO 0x4a002558
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#define QSPI_CMD_READ (0x3 << 0)
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#define QSPI_CMD_READ_QUAD (0x6b << 0)
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#define QSPI_CMD_READ_FAST (0x0b << 0)
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#define QSPI_SETUP0_NUM_A_BYTES (0x2 << 8)
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#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
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#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
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#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
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#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
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#define QSPI_CMD_WRITE (0x2 << 16)
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#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
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/* ti qspi register set */
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struct ti_qspi_regs {
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u32 pid;
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u32 pad0[3];
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u32 sysconfig;
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u32 pad1[3];
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u32 int_stat_raw;
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u32 int_stat_en;
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u32 int_en_set;
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u32 int_en_ctlr;
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u32 intc_eoi;
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u32 pad2[3];
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u32 clk_ctrl;
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u32 dc;
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u32 cmd;
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u32 status;
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u32 data;
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u32 setup0;
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u32 setup1;
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u32 setup2;
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u32 setup3;
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u32 memswitch;
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u32 data1;
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u32 data2;
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u32 data3;
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};
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/* ti qspi slave */
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struct ti_qspi_slave {
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struct spi_slave slave;
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struct ti_qspi_regs *base;
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unsigned int mode;
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u32 cmd;
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u32 dc;
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};
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static inline struct ti_qspi_slave *to_ti_qspi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct ti_qspi_slave, slave);
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}
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static void ti_spi_setup_spi_register(struct ti_qspi_slave *qslave)
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{
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struct spi_slave *slave = &qslave->slave;
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u32 memval = 0;
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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slave->memory_map = (void *)MMAP_START_ADDR_DRA;
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#else
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slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
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#endif
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#ifdef CONFIG_QSPI_QUAD_SUPPORT
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memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_8_BITS |
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QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS);
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slave->op_mode_rx = SPI_OPM_RX_QOF;
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#else
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
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QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS;
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#endif
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writel(memval, &qslave->base->setup0);
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}
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static void ti_spi_set_speed(struct spi_slave *slave, uint hz)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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uint clk_div;
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debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
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if (!hz)
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clk_div = 0;
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else
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clk_div = (QSPI_FCLK / hz) - 1;
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/* disable SCLK */
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writel(readl(&qslave->base->clk_ctrl) & ~QSPI_CLK_EN,
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&qslave->base->clk_ctrl);
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/* assign clk_div values */
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if (clk_div < 0)
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clk_div = 0;
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else if (clk_div > QSPI_CLK_DIV_MAX)
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clk_div = QSPI_CLK_DIV_MAX;
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/* enable SCLK */
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writel(QSPI_CLK_EN | clk_div, &qslave->base->clk_ctrl);
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* CS handled in xfer */
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return;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
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writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
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/* dummy readl to ensure bus sync */
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readl(&qslave->base->cmd);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ti_qspi_slave *qslave;
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#ifdef CONFIG_AM43XX
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
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#endif
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qslave = spi_alloc_slave(struct ti_qspi_slave, bus, cs);
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if (!qslave) {
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printf("SPI_error: Fail to allocate ti_qspi_slave\n");
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return NULL;
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}
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qslave->base = (struct ti_qspi_regs *)QSPI_BASE;
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qslave->mode = mode;
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ti_spi_set_speed(&qslave->slave, max_hz);
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#ifdef CONFIG_TI_SPI_MMAP
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ti_spi_setup_spi_register(qslave);
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#endif
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return &qslave->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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free(qslave);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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qslave->dc = 0;
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if (qslave->mode & SPI_CPHA)
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qslave->dc |= QSPI_CKPHA(slave->cs);
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if (qslave->mode & SPI_CPOL)
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qslave->dc |= QSPI_CKPOL(slave->cs);
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if (qslave->mode & SPI_CS_HIGH)
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qslave->dc |= QSPI_CSPOL(slave->cs);
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writel(qslave->dc, &qslave->base->dc);
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writel(0, &qslave->base->cmd);
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writel(0, &qslave->base->data);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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writel(0, &qslave->base->dc);
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writel(0, &qslave->base->cmd);
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writel(0, &qslave->base->data);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct ti_qspi_slave *qslave = to_ti_qspi_slave(slave);
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uint words = bitlen >> 3; /* fixed 8-bit word length */
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const uchar *txp = dout;
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uchar *rxp = din;
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uint status;
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int timeout;
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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int val;
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#endif
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debug("spi_xfer: bus:%i cs:%i bitlen:%i words:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, words, flags);
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/* Setup mmap flags */
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if (flags & SPI_XFER_MMAP) {
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writel(MM_SWITCH, &qslave->base->memswitch);
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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val = readl(CORE_CTRL_IO);
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val |= MEM_CS;
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writel(val, CORE_CTRL_IO);
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#endif
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return 0;
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} else if (flags & SPI_XFER_MMAP_END) {
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writel(~MM_SWITCH, &qslave->base->memswitch);
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#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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val = readl(CORE_CTRL_IO);
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val &= MEM_CS_UNSELECT;
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writel(val, CORE_CTRL_IO);
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#endif
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return 0;
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}
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if (bitlen == 0)
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return -1;
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if (bitlen % 8) {
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debug("spi_xfer: Non byte aligned SPI transfer\n");
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return -1;
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}
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/* Setup command reg */
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qslave->cmd = 0;
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qslave->cmd |= QSPI_WLEN(8);
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qslave->cmd |= QSPI_EN_CS(slave->cs);
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if (flags & SPI_3WIRE)
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qslave->cmd |= QSPI_3_PIN;
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qslave->cmd |= 0xfff;
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/* FIXME: This delay is required for successfull
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* completion of read/write/erase. Once its root
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* caused, it will be remove from the driver.
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*/
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#ifdef CONFIG_AM43XX
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udelay(100);
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#endif
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while (words--) {
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if (txp) {
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debug("tx cmd %08x dc %08x data %02x\n",
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qslave->cmd | QSPI_WR_SNGL, qslave->dc, *txp);
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writel(*txp++, &qslave->base->data);
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writel(qslave->cmd | QSPI_WR_SNGL,
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&qslave->base->cmd);
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status = readl(&qslave->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: TX timeout!\n");
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return -1;
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}
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status = readl(&qslave->base->status);
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}
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debug("tx done, status %08x\n", status);
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}
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if (rxp) {
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qslave->cmd |= QSPI_RD_SNGL;
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debug("rx cmd %08x dc %08x\n",
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qslave->cmd, qslave->dc);
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#ifdef CONFIG_DRA7XX
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udelay(500);
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#endif
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writel(qslave->cmd, &qslave->base->cmd);
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status = readl(&qslave->base->status);
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timeout = QSPI_TIMEOUT;
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while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) {
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if (--timeout < 0) {
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printf("spi_xfer: RX timeout!\n");
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return -1;
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}
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status = readl(&qslave->base->status);
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}
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*rxp++ = readl(&qslave->base->data);
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debug("rx done, status %08x, read %02x\n",
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status, *(rxp-1));
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}
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}
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/* Terminate frame */
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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/* TODO: control from sf layer to here through dm-spi */
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#ifdef CONFIG_TI_EDMA3
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void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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{
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unsigned int addr = (unsigned int) (data);
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unsigned int edma_slot_num = 1;
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/* Invalidate the area, so no writeback into the RAM races with DMA */
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invalidate_dcache_range(addr, addr + roundup(len, ARCH_DMA_MINALIGN));
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/* enable edma3 clocks */
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enable_edma3_clocks();
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/* Call edma3 api to do actual DMA transfer */
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edma3_transfer(EDMA3_BASE, edma_slot_num, data, offset, len);
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/* disable edma3 clocks */
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disable_edma3_clocks();
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*((unsigned int *)offset) += len;
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}
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#endif
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