Simon Glass 90b16d1491 x86: chromebook_link: dts: Add PCH and LPC devices ... The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>		2015-04-18 11:11:15 -06:00
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include	Makefile: Support include files for .dts files	2014-06-20 11:55:03 -06:00
microcode	x86: Add support for Intel Minnowboard Max	2015-02-06 12:07:39 -07:00
.gitignore	dts: generate multiple device tree blobs	2014-02-19 11:10:05 -05:00
chromebook_link.dts	x86: chromebook_link: dts: Add PCH and LPC devices	2015-04-18 11:11:15 -06:00
chromebox_panther.dts	x86: Add support for panther (Asus Chromebox)	2015-04-16 19:27:40 -06:00
crownbay.dts	x86: crownbay: Add pci devices in the dts file	2015-01-13 07:24:57 -08:00
galileo.dts	x86: Add SPI support to quark/galileo	2015-02-06 12:07:45 -07:00
Makefile	x86: Add support for panther (Asus Chromebox)	2015-04-16 19:27:40 -06:00
minnowmax.dts	x86: Add support for Intel Minnowboard Max	2015-02-06 12:07:39 -07:00
serial.dtsi	x86: Add support for Intel Minnowboard Max	2015-02-06 12:07:39 -07:00
skeleton.dtsi	x86: fdt: Create basic .dtsi file for coreboot	2012-12-06 14:30:42 -08:00