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https://github.com/brain-hackers/u-boot-brain
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909a1ab2f0
Move USB controller Base address mapping from ls102xa immap to fsl xhci header. This is required to remove any warnings when controller base addresses are mapped for multiple platforms in their respective files. Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* FSL USB HOST xHCI Controller
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*
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* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_XHCI_FSL_H_
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#define _ASM_ARCH_XHCI_FSL_H_
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/* Default to the FSL XHCI defines */
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#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
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#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
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#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
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#define USB3_PHY_RX_POWERON BIT(14)
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#define USB3_PHY_TX_POWERON BIT(15)
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#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
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#define USB3_PWRCTL_CLK_CMD_SHIFT 14
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#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
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/* USBOTGSS_WRAPPER definitions */
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#define USBOTGSS_WRAPRESET BIT(17)
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#define USBOTGSS_DMADISABLE BIT(16)
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#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
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#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
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#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
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#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
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#define USBOTGSS_IDLEMODE_SMRT BIT(3)
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#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
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/* USBOTGSS_IRQENABLE_SET_0 bit */
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#define USBOTGSS_COREIRQ_EN BIT(1)
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/* USBOTGSS_IRQENABLE_SET_1 bits */
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
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#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
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#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
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#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
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#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
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#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
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#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
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struct fsl_xhci {
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struct xhci_hccr *hcd;
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struct dwc3 *dwc3_reg;
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};
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#if defined(CONFIG_LS102XA)
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#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
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#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
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#endif
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#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
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CONFIG_SYS_FSL_XHCI_USB2_ADDR}
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#endif /* _ASM_ARCH_XHCI_FSL_H_ */
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