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https://github.com/brain-hackers/u-boot-brain
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fbfd92bf9b
U-Boot SPL can be run in a different privilege mode from U-Boot proper. Add new configuration entries for SPL to allow the run mode to be configured independently of U-Boot proper. Extend all uses of the CONFIG_RISCV_SMODE and CONFIG_RISCV_MMODE configuration symbols to also cover the SPL equivalents. Ensure that files compatible with only one privilege mode are not included in builds targeting an incompatible privilege mode. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
106 lines
2.2 KiB
C
106 lines
2.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/encoding.h>
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#include <dm/uclass-internal.h>
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/*
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* The variables here must be stored in the data section since they are used
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* before the bss section is available.
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*/
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#ifdef CONFIG_OF_PRIOR_STAGE
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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#endif
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#ifndef CONFIG_XIP
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u32 hart_lottery __attribute__((section(".data"))) = 0;
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/*
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* The main hart running U-Boot has acquired available_harts_lock until it has
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* finished initialization of global data.
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*/
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u32 available_harts_lock = 1;
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#endif
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static inline bool supports_extension(char ext)
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{
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#ifdef CONFIG_CPU
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struct udevice *dev;
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char desc[32];
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uclass_find_first_device(UCLASS_CPU, &dev);
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if (!dev) {
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debug("unable to find the RISC-V cpu device\n");
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return false;
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}
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if (!cpu_get_desc(dev, desc, sizeof(desc))) {
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/* skip the first 4 characters (rv32|rv64) */
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if (strchr(desc + 4, ext))
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return true;
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}
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return false;
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#else /* !CONFIG_CPU */
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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return csr_read(CSR_MISA) & (1 << (ext - 'a'));
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#else /* !CONFIG_IS_ENABLED(RISCV_MMODE) */
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#warning "There is no way to determine the available extensions in S-mode."
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#warning "Please convert your board to use the RISC-V CPU driver."
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return false;
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#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */
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#endif /* CONFIG_CPU */
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}
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static int riscv_cpu_probe(void)
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{
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#ifdef CONFIG_CPU
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int ret;
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/* probe cpus so that RISC-V timer can be bound */
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ret = cpu_probe_all();
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if (ret)
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return log_msg_ret("RISC-V cpus probe failed\n", ret);
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#endif
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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int ret;
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ret = riscv_cpu_probe();
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if (ret)
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return ret;
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/* Enable FPU */
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if (supports_extension('d') || supports_extension('f')) {
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csr_set(MODE_PREFIX(status), MSTATUS_FS);
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csr_write(CSR_FCSR, 0);
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}
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if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
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/*
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* Enable perf counters for cycle, time,
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* and instret counters only
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*/
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csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
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/* Disable paging */
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if (supports_extension('s'))
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csr_write(CSR_SATP, 0);
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}
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return 0;
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}
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int arch_early_init_r(void)
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{
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return riscv_cpu_probe();
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}
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