mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
9e0bb4c1d9
Enable UUID and GPT partition support for NXP's ARM based SoCs i.e. LS1012A, LS1021A, LS1043A, LS1046A and LS2080A. Also enable DOS partition for LS1012AFRDM boards. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
320 lines
9.5 KiB
C
320 lines
9.5 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1043ARDB_H__
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#define __LS1043ARDB_H__
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#include "ls1043a_common.h"
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#if defined(CONFIG_FSL_LS_PPA)
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#define CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
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#define SEC_FIRMWARE_ERET_ADDR_REVERT
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#define CONFIG_SYS_LS_PPA_FW_IN_XIP
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#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
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#define CONFIG_SYS_LS_PPA_FW_ADDR 0x60500000
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#endif
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#endif
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#if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
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#define CONFIG_SYS_TEXT_BASE 0x82000000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x60100000
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#endif
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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#define CONFIG_MISC_INIT_R
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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/* Physical Memory Map */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_SYS_SPD_BUS_NUM 0
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#define CONFIG_FSL_DDR_BIST
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#define CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
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#endif
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
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#endif
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#ifdef CONFIG_SD_BOOT
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#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg
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#endif
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/*
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* NOR Flash Definitions
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*/
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#define CONFIG_SYS_NOR_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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#define CONFIG_SYS_NOR_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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/* NOR Flash Timing Params */
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#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_TRHZ_80)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TAVDS(0x0) | \
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FTIM0_NOR_TEAHC(0xc))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \
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FTIM1_NOR_TRAD_NOR(0xb) | \
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FTIM1_NOR_TSEQRAD_NOR(0x9))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x8) | \
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FTIM2_NOR_TWP(0x10))
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#define CONFIG_SYS_NOR_FTIM3 0
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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/*
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* NAND Flash Definitions
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*/
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_NAND_BASE 0x7e800000
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#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x7) | \
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FTIM0_NAND_TWH(0xa))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0xe) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
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FTIM2_NAND_TREH(0xa) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */
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#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10)
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#endif
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/*
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* CPLD
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*/
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#define CONFIG_SYS_CPLD_BASE 0x7fb00000
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#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
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#define CONFIG_SYS_CPLD_CSPR_EXT (0x0)
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#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
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CSPR_PORT_SIZE_8 | \
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CSPR_MSEL_GPCM | \
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CSPR_V)
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#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
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CSOR_NOR_NOR_MODE_AVD_NOR | \
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CSOR_NOR_TRHZ_80)
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/* CPLD Timing parameters for IFC GPCM */
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#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
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FTIM0_GPCM_TEADC(0xf) | \
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FTIM0_GPCM_TEAHC(0xf))
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#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0xff))
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#define CONFIG_SYS_CPLD_FTIM3 0x0
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/* IFC Timing Params */
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#ifdef CONFIG_NAND_BOOT
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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#endif
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SD_BOOT)
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#define CONFIG_ENV_OFFSET (1024 * 1024)
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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/* FMan */
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHYLIB
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#define CONFIG_PHYLIB_10G
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#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
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#define CONFIG_PHY_VITESSE
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#define CONFIG_PHY_REALTEK
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#define CONFIG_PHY_AQUANTIA
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#define AQR105_IRQ_MASK 0x40000000
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#define RGMII_PHY1_ADDR 0x1
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#define RGMII_PHY2_ADDR 0x2
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#define QSGMII_PORT1_PHY_ADDR 0x4
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#define QSGMII_PORT2_PHY_ADDR 0x5
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#define QSGMII_PORT3_PHY_ADDR 0x6
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#define QSGMII_PORT4_PHY_ADDR 0x7
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#define FM1_10GEC1_PHY_ADDR 0x1
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#define CONFIG_ETHPRIME "FM1@DTSEC3"
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#endif
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/* QE */
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
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!defined(CONFIG_QSPI_BOOT)
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#define CONFIG_U_QE
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#endif
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#define CONFIG_SYS_QE_FW_ADDR 0x60600000
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/* USB */
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#define CONFIG_HAS_FSL_XHCI_USB
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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#define CONFIG_USB_XHCI_FSL
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#endif
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/* SATA */
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_CMD_SCSI
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#ifndef CONFIG_CMD_FAT
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#define CONFIG_CMD_FAT
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#endif
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#ifndef CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT2
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#endif
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#define CONFIG_DOS_PARTITION
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2
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#define CONFIG_SYS_SCSI_MAX_LUN 2
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#define SCSI_VEND_ID 0x1b4b
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#define SCSI_DEV_ID 0x9170
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#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID}
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#define CONFIG_PARTITION_UUIDS
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#define CONFIG_EFI_PARTITION
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#define CONFIG_CMD_GPT
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS1043ARDB_H__ */
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