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https://github.com/brain-hackers/u-boot-brain
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904110c7ac
Up to now, there are 3 kind of SoCs under Layerscape Chassis 2, like LS1043A, LS1046A and LS1012A. But the clocks tree has a lot of differences, for instance, the IP modules have different dividers to derive its clock from Platform PLL. And the core cluster PLL and platform PLL maybe have different reference clocks, such as LS1012A. Another problem is which clock/PLL should be described by sys_info->freq_systembus, it is confused in Layerscape Chissis 2. This patch is to bind the sys_info->freq_systembus to the Platform PLL, and handle the different divider of IP modules separately between different SoCs, and separate reference clocks of core cluster PLL and platform PLL. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> |
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| .. | ||
| fsl-layerscape | ||
| hisilicon | ||
| s32v234 | ||
| zynqmp | ||
| cache_v8.c | ||
| cache.S | ||
| config.mk | ||
| cpu-dt.c | ||
| cpu.c | ||
| exceptions.S | ||
| fwcall.c | ||
| generic_timer.c | ||
| Kconfig | ||
| Makefile | ||
| psci.S | ||
| sec_firmware_asm.S | ||
| sec_firmware.c | ||
| spin_table_v8.S | ||
| spin_table.c | ||
| start.S | ||
| tlb.S | ||
| transition.S | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||