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https://github.com/brain-hackers/u-boot-brain
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fe60f06dcd
Implement a reset uclass driver for the Tegra CAR. This allows clients to use standard reset APIs on Tegra. This device is intended to be instantiated by the core Tegra CAR driver, rather than being instantiated directly from DT. The implementation uses the existing custom Tegra- specific reset APIs to avoid coupling the series with significant refactoring of the existing Tegra clock/reset code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
38 lines
1.3 KiB
Plaintext
38 lines
1.3 KiB
Plaintext
menu "Reset Controller Support"
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config DM_RESET
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bool "Enable reset controllers using Driver Model"
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depends on DM && OF_CONTROL
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help
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Enable support for the reset controller driver class. Many hardware
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modules are equipped with a reset signal, typically driven by some
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reset controller hardware module within the chip. In U-Boot, reset
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controller drivers allow control over these reset signals. In some
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cases this API is applicable to chips outside the CPU as well,
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although driving such reset isgnals using GPIOs may be more
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appropriate in this case.
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config SANDBOX_RESET
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bool "Enable the sandbox reset test driver"
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depends on DM_MAILBOX && SANDBOX
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help
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Enable support for a test reset controller implementation, which
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simply accepts requests to reset various HW modules without actually
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doing anything beyond a little error checking.
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config TEGRA_CAR_RESET
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bool "Enable Tegra CAR-based reset driver"
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depends on TEGRA_CAR
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help
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Enable support for manipulating Tegra's on-SoC reset signals via
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direct register access to the Tegra CAR (Clock And Reset controller).
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config TEGRA186_RESET
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bool "Enable Tegra186 BPMP-based reset driver"
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depends on TEGRA186_BPMP
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help
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Enable support for manipulating Tegra's on-SoC reset signals via IPC
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requests to the BPMP (Boot and Power Management Processor).
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endmenu
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