mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 17:38:51 +09:00
![Alexander Graf](/assets/img/avatar_default.png)
We only need u-boot to bother about a single core in the QEMU machine. Everything that would require additional knowledge of more cores gets handled by QEMU and passed straight into the payload we execute. Because of this setup, it would be counterproductive to enable SMP support in u-boot. We would have to rip CPUs out of already existing spin tables and respin them from u-boot. It would be a pretty big mess. So only assume we have a single core. This fixes errors about CONFIG_MP being disabled. Signed-off-by: Alexander Graf <agraf@suse.de>
369 lines
7.6 KiB
C
369 lines
7.6 KiB
C
/*
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* Copyright 2007,2009-2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/fsl_pci.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <netdev.h>
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#include <fdtdec.h>
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#include <errno.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void *get_fdt_virt(void)
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{
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return (void *)CONFIG_SYS_TMPVIRT;
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}
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static uint64_t get_fdt_phys(void)
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{
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return (uint64_t)(uintptr_t)gd->fdt_blob;
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}
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static void map_fdt_as(int esel)
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{
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u32 mas0, mas1, mas2, mas3, mas7;
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uint64_t fdt_phys = get_fdt_phys();
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unsigned long fdt_phys_tlb = fdt_phys & ~0xffffful;
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unsigned long fdt_virt_tlb = (ulong)get_fdt_virt() & ~0xffffful;
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mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(esel);
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mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
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mas2 = FSL_BOOKE_MAS2(fdt_virt_tlb, 0);
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mas3 = FSL_BOOKE_MAS3(fdt_phys_tlb, 0, MAS3_SW|MAS3_SR);
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mas7 = FSL_BOOKE_MAS7(fdt_phys_tlb);
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write_tlb(mas0, mas1, mas2, mas3, mas7);
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}
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uint64_t get_phys_ccsrbar_addr_early(void)
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{
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void *fdt = get_fdt_virt();
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uint64_t r;
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/*
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* To be able to read the FDT we need to create a temporary TLB
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* map for it.
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*/
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map_fdt_as(10);
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r = fdt_get_base_address(fdt, fdt_path_offset(fdt, "/soc"));
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disable_tlb(10);
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return r;
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}
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int board_early_init_f(void)
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{
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return 0;
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}
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int checkboard(void)
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{
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return 0;
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}
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static int pci_map_region(void *fdt, int pci_node, int range_id,
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phys_size_t *ppaddr, pci_addr_t *pvaddr,
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pci_size_t *psize, ulong *pmap_addr)
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{
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uint64_t addr;
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uint64_t size;
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ulong map_addr;
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int r;
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r = fdt_read_range(fdt, pci_node, 0, NULL, &addr, &size);
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if (r)
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return r;
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if (ppaddr)
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*ppaddr = addr;
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if (psize)
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*psize = size;
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if (!pmap_addr)
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return 0;
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map_addr = *pmap_addr;
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/* Align map_addr */
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map_addr += size - 1;
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map_addr &= ~(size - 1);
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if (map_addr + size >= CONFIG_SYS_PCI_MAP_END)
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return -1;
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/* Map virtual memory for range */
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assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
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*pmap_addr = map_addr + size;
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if (pvaddr)
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*pvaddr = map_addr;
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return 0;
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}
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void pci_init_board(void)
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{
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struct pci_controller *pci_hoses;
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void *fdt = get_fdt_virt();
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int pci_node = -1;
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int pci_num = 0;
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int pci_count = 0;
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ulong map_addr;
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puts("\n");
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/* Start MMIO and PIO range maps above RAM */
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map_addr = CONFIG_SYS_PCI_MAP_START;
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/* Count and allocate PCI buses */
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pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
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"device_type", "pci", 4);
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while (pci_node != -FDT_ERR_NOTFOUND) {
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pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
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"device_type", "pci", 4);
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pci_count++;
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}
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if (pci_count) {
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pci_hoses = malloc(sizeof(struct pci_controller) * pci_count);
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} else {
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printf("PCI: disabled\n\n");
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return;
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}
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/* Spawn PCI buses based on device tree */
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pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
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"device_type", "pci", 4);
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while (pci_node != -FDT_ERR_NOTFOUND) {
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struct fsl_pci_info pci_info = { };
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const fdt32_t *reg;
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int r;
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reg = fdt_getprop(fdt, pci_node, "reg", NULL);
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pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
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/* Map MMIO range */
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r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
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&pci_info.mem_size, &map_addr);
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if (r)
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break;
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/* Map PIO range */
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r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
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&pci_info.io_size, &map_addr);
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if (r)
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break;
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/*
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* The PCI framework finds virtual addresses for the buses
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* through our address map, so tell it the physical addresses.
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*/
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pci_info.mem_bus = pci_info.mem_phys;
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pci_info.io_bus = pci_info.io_phys;
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/* Instantiate */
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pci_info.pci_num = pci_num + 1;
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fsl_setup_hose(&pci_hoses[pci_num], pci_info.regs);
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printf("PCI: base address %lx\n", pci_info.regs);
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fsl_pci_init_port(&pci_info, &pci_hoses[pci_num], pci_num);
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/* Jump to next PCI node */
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pci_node = fdt_node_offset_by_prop_value(fdt, pci_node,
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"device_type", "pci", 4);
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pci_num++;
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}
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puts("\n");
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}
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int last_stage_init(void)
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{
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void *fdt = get_fdt_virt();
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int len = 0;
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const uint64_t *prop;
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int chosen;
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chosen = fdt_path_offset(fdt, "/chosen");
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if (chosen < 0) {
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printf("Couldn't find /chosen node in fdt\n");
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return -EIO;
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}
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/* -kernel boot */
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prop = fdt_getprop(fdt, chosen, "qemu,boot-kernel", &len);
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if (prop && (len >= 8))
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setenv_hex("qemu_kernel_addr", *prop);
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/* Give the user a variable for the host fdt */
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setenv_hex("fdt_addr_r", (ulong)fdt);
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return 0;
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}
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static uint64_t get_linear_ram_size(void)
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{
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void *fdt = get_fdt_virt();
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const void *prop;
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int memory;
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int len;
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memory = fdt_path_offset(fdt, "/memory");
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prop = fdt_getprop(fdt, memory, "reg", &len);
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if (prop && len >= 16)
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return *(uint64_t *)(prop+8);
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panic("Couldn't determine RAM size");
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}
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int board_eth_init(bd_t *bis)
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{
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return pci_eth_init(bis);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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FT_FSL_PCI_SETUP;
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}
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#endif
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void print_laws(void)
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{
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/* We don't emulate LAWs yet */
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}
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phys_size_t fixed_sdram(void)
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{
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return get_linear_ram_size();
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}
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phys_size_t fsl_ddr_sdram_size(void)
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{
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return get_linear_ram_size();
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}
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void init_tlbs(void)
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{
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phys_size_t ram_size;
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/*
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* Create a temporary AS=1 map for the fdt
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*
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* We use ESEL=0 here to overwrite the previous AS=0 map for ourselves
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* which was only 4k big. This way we don't have to clear any other maps.
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*/
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map_fdt_as(0);
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/* Fetch RAM size from the fdt */
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ram_size = get_linear_ram_size();
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/* And remove our fdt map again */
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disable_tlb(0);
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/* Create an internal map of manually created TLB maps */
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init_used_tlb_cams();
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/* Create a dynamic AS=0 CCSRBAR mapping */
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assert(!tlb_map_range(CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
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1024 * 1024, TLB_MAP_IO));
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/* Create a RAM map that spans all accessible RAM */
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setup_ddr_tlbs(ram_size >> 20);
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/* Create a map for the TLB */
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assert(!tlb_map_range((ulong)get_fdt_virt(), get_fdt_phys(),
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1024 * 1024, TLB_MAP_RAM));
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}
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void init_laws(void)
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{
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/* We don't emulate LAWs yet */
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}
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static uint32_t get_cpu_freq(void)
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{
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void *fdt = get_fdt_virt();
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int cpus_node = fdt_path_offset(fdt, "/cpus");
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int cpu_node = fdt_first_subnode(fdt, cpus_node);
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const char *prop = "clock-frequency";
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return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
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}
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void get_sys_info(sys_info_t *sys_info)
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{
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int freq = get_cpu_freq();
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memset(sys_info, 0, sizeof(sys_info_t));
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sys_info->freq_systembus = freq;
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sys_info->freq_ddrbus = freq;
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sys_info->freq_processor[0] = freq;
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}
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int get_clocks (void)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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gd->cpu_clk = sys_info.freq_processor[0];
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gd->bus_clk = sys_info.freq_systembus;
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gd->mem_clk = sys_info.freq_ddrbus;
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gd->arch.lbc_clk = sys_info.freq_ddrbus;
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return 0;
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}
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unsigned long get_tbclk (void)
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{
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void *fdt = get_fdt_virt();
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int cpus_node = fdt_path_offset(fdt, "/cpus");
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int cpu_node = fdt_first_subnode(fdt, cpus_node);
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const char *prop = "timebase-frequency";
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return fdt_getprop_u32_default_node(fdt, cpu_node, 0, prop, 0);
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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sys_info_t sys_info;
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get_sys_info(&sys_info);
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return sys_info.freq_systembus;
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}
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/*
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* Return the number of cores on this SOC.
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*/
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int cpu_numcores(void)
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{
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/*
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* The QEMU u-boot target only needs to drive the first core,
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* spinning and device tree nodes get driven by QEMU itself
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*/
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return 1;
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}
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/*
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* Return a 32-bit mask indicating which cores are present on this SOC.
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*/
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u32 cpu_mask(void)
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{
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return (1 << cpu_numcores()) - 1;
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}
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