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https://github.com/brain-hackers/u-boot-brain
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72a087e047
Patch by Haavard Skinnemoen, 06 Sep 2006 This patch adds support for the AT32AP CPU family and the AT32AP7000 chip, which is the first chip implementing the AVR32 architecture. The AT32AP CPU core is a high-performance implementation featuring a 7-stage pipeline, separate instruction- and data caches, and a MMU. For more information, please see the "AVR32 AP Technical Reference": http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf In addition to this, the AT32AP7000 chip comes with a large set of integrated peripherals, many of which are shared with the AT91 series of ARM-based microcontrollers from Atmel. Full data sheet is available here: http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
62 lines
2.9 KiB
C
62 lines
2.9 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
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#define __ASM_AVR32_PART_MEMORY_MAP_H__
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#define AUDIOC_BASE 0xFFF02800
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#define DAC_BASE 0xFFF02000
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#define DMAC_BASE 0xFF200000
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#define ECC_BASE 0xFFF03C00
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#define HISI_BASE 0xFFF02C00
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#define HMATRIX_BASE 0xFFF00800
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#define HSDRAMC_BASE 0xFFF03800
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#define HSMC_BASE 0xFFF03400
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#define LCDC_BASE 0xFF000000
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#define MACB0_BASE 0xFFF01800
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#define MACB1_BASE 0xFFF01C00
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#define MMCI_BASE 0xFFF02400
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#define PIOA_BASE 0xFFE02800
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#define PIOB_BASE 0xFFE02C00
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#define PIOC_BASE 0xFFE03000
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#define PIOD_BASE 0xFFE03400
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#define PIOE_BASE 0xFFE03800
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#define PSIF_BASE 0xFFE03C00
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#define PWM_BASE 0xFFF01400
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#define SM_BASE 0xFFF00000
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#define INTC_BASE 0XFFF00400
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#define SPI0_BASE 0xFFE00000
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#define SPI1_BASE 0xFFE00400
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#define SSC0_BASE 0xFFE01C00
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#define SSC1_BASE 0xFFE02000
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#define SSC2_BASE 0xFFE02400
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#define TIMER0_BASE 0xFFF00C00
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#define TIMER1_BASE 0xFFF01000
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#define TWI_BASE 0xFFE00800
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#define USART0_BASE 0xFFE00C00
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#define USART1_BASE 0xFFE01000
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#define USART2_BASE 0xFFE01400
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#define USART3_BASE 0xFFE01800
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#define USB_FIFO 0xFF300000
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#define USB_BASE 0xFFF03000
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#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
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