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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 08:28:51 +09:00
348 lines
8.3 KiB
C
348 lines
8.3 KiB
C
/*
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* Faraday FTIDE020 ATA Controller (AHB)
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*
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* (C) Copyright 2011 Andes Technology
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* Greentime Hu <greentime@andestech.com>
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* Macpaul Lin <macpaul@andestech.com>
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* Kuo-Wei Chou <kwchou@andestech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* ftide020.c - ide support functions for the FTIDE020_S controller */
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#include <config.h>
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#include <common.h>
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#include <ata.h>
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#include <ide.h>
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#include <asm/io.h>
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#include <api_public.h>
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#include "ftide020.h"
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/* base address */
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#define FTIDE_BASE CONFIG_SYS_ATA_BASE_ADDR
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/*
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* data address - The CMD and DATA use the same FIFO in FTIDE020_S
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* FTIDE_DATA = CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_DATA_OFFSET
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* = &ftide020->rw_fifo
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*/
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#define FTIDE_DATA (&ftide020->rw_fifo)
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/* command and data I/O macros */
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/* 0x0 - DATA FIFO */
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#define WRITE_DATA(x) outl((x), &ftide020->rw_fifo) /* 0x00 */
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#define READ_DATA() inl(&ftide020->rw_fifo) /* 0x00 */
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/* 0x04 - R: Status Reg, W: CMD_FIFO */
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#define WRITE_CMD(x) outl((x), &ftide020->cmd_fifo) /* 0x04 */
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#define READ_STATUS() inl(&ftide020->cmd_fifo) /* 0x04 */
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void ftide_set_device(int cx8, int dev)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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WRITE_CMD(SET_DEV_CMD | IDE_SET_CX8(cx8) | dev);
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}
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unsigned char ide_read_register(int dev, unsigned int port)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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ftide_set_device(0, dev);
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WRITE_CMD(READ_REG_CMD | IDE_REG_CS_READ(CONFIG_IDE_REG_CS) |
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IDE_REG_DA_WRITE(port));
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return READ_DATA() & 0xff;
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}
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void ide_write_register(int dev, unsigned int port, unsigned char val)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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ftide_set_device(0, dev);
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WRITE_CMD(WRITE_REG_CMD | IDE_REG_CS_WRITE(CONFIG_IDE_REG_CS) |
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IDE_REG_DA_WRITE(port) | val);
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}
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void ide_write_data(int dev, const ulong *sect_buf, int words)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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ftide_set_device(0, dev);
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WRITE_CMD(WRITE_DATA_CMD | ((words << 2) - 1));
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/* block write */
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outsl(FTIDE_DATA, sect_buf, words);
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}
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void ide_read_data(int dev, ulong *sect_buf, int words)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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ftide_set_device(0, dev);
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WRITE_CMD(READ_DATA_CMD | ((words << 2) - 1));
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/* block read */
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insl(FTIDE_DATA, sect_buf, words);
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}
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void ftide_dfifo_ready(ulong *time)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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while (!(READ_STATUS() & STATUS_RFE)) {
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if (*time-- == 0)
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break;
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udelay(100);
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}
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}
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extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
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/* Reset_IDE_controller */
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static void reset_ide_controller(void)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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unsigned int val;
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val = inl(&ftide020->cr);
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val |= CONTROL_RST;
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outl(val, &ftide020->cr);
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/* wait until reset OK, this is poor HW design */
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mdelay(50);
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val &= ~(CONTROL_RST);
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outl(val, &ftide020->cr);
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mdelay(50);
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val |= CONTROL_SRST;
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outl(val, &ftide020->cr);
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/* wait until reset OK, this is poor HW design */
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mdelay(50);
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val &= ~(CONTROL_SRST);
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outl(val, &ftide020->cr);
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/* IORDY enable for PIO, for 2 device */
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val |= (CONTROL_IRE0 | CONTROL_IRE1);
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outl(val, &ftide020->cr);
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}
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/* IDE clock frequence */
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uint ftide_clock_freq(void)
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{
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/*
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* todo: To aquire dynamic system frequency is dependend on the power
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* management unit which the ftide020 is connected to. In current,
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* there are only few PMU supports in u-boot.
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* So this function is wait for future enhancement.
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*/
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return 100;
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}
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/* Calculate Timing Registers */
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static unsigned int timing_cal(u16 t0, u16 t1, u16 t2, u16 t4)
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{
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unsigned int val, ahb_ns = 8;
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u8 TEOC, T1, T2, T4;
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T1 = (u8) (t1 / ahb_ns);
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if ((T1 * ahb_ns) == t1)
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T1--;
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T2 = (u8) (t2 / ahb_ns);
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if ((T2 * ahb_ns) == t2)
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T2--;
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T4 = (u8) (t4 / ahb_ns);
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if ((T4 * ahb_ns) == t4)
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T4--;
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TEOC = (u8) (t0 / ahb_ns);
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if ((TEOC * ahb_ns) == t0)
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TEOC--;
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TEOC = ((TEOC > (T1 + T2 + T4)) ? (TEOC - (T1 + T2 + T4)) : 0);
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/*
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* Here the fields in data timing registers in PIO mode
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* is accessed the same way as command timing registers.
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*/
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val = DT_REG_PIO_T1(T1) |
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DT_REG_PIO_T2(T2) |
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DT_REG_PIO_T4(T4) |
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DT_REG_PIO_TEOC(TEOC);
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return val;
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}
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/* Set Timing Register */
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static unsigned int set_mode_timing(u8 dev, u8 id, u8 mode)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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u16 t0, t1, t2, t4;
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u8 tcyc, tcvs, tmli, tenv, tack, trp;
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unsigned int val, sysclk = 8;
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if (id >= TATOL_TIMING)
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return 0;
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sysclk = ftide_clock_freq();
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switch (id) {
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case CMD_TIMING:
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if (mode < REG_MODE) {
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t0 = REG_ACCESS_TIMING[REG_T0][mode];
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t1 = REG_ACCESS_TIMING[REG_T1][mode];
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t2 = REG_ACCESS_TIMING[REG_T2][mode];
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t4 = REG_ACCESS_TIMING[REG_T4][mode];
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val = timing_cal(t0, t1, t2, t4);
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outl(val, (dev ? &ftide020->ctrd1 : &ftide020->ctrd0));
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return 1;
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} else
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return 0;
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case PIO_TIMING:
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if (mode < PIO_MODE) {
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t0 = PIO_ACCESS_TIMING[PIO_T0][mode];
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t1 = PIO_ACCESS_TIMING[PIO_T1][mode];
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t2 = PIO_ACCESS_TIMING[PIO_T2][mode];
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t4 = PIO_ACCESS_TIMING[PIO_T4][mode];
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val = timing_cal(t0, t1, t2, t4);
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outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
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return 1;
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} else
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return 0;
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case DMA_TIMING:
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if (mode < UDMA_MODE) {
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/*
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* 0.999 is ceiling
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* for tcyc, tcvs, tmli, tenv, trp, tack
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*/
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tcyc = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCYC][mode] \
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* sysclk) + 9990) / 10000);
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tcvs = (u8) (((UDMA_ACCESS_TIMING[UDMA_TCVS][mode] \
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* sysclk) + 9990) / 10000);
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tmli = (u8) (((UDMA_ACCESS_TIMING[UDMA_TMLI][mode] \
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* sysclk) + 9990) / 10000);
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tenv = (u8) (((UDMA_ACCESS_TIMING[UDMA_TENV][mode] \
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* sysclk) + 9990) / 10000);
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trp = (u8) (((UDMA_ACCESS_TIMING[UDMA_TRP][mode] \
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* sysclk) + 9990) / 10000);
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tack = (u8) (((UDMA_ACCESS_TIMING[UDMA_TACK][mode] \
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* sysclk) + 9990) / 10000);
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val = DT_REG_UDMA_TENV((tenv > 0) ? (tenv - 1) : 0) |
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DT_REG_UDMA_TMLI((tmli > 0) ? (tmli - 1) : 0) |
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DT_REG_UDMA_TCYC((tcyc > 0) ? (tcyc - 1) : 0) |
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DT_REG_UDMA_TACK((tack > 0) ? (tack - 1) : 0) |
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DT_REG_UDMA_TCVS((tcvs > 0) ? (tcvs - 1) : 0) |
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DT_REG_UDMA_TRP((trp > 0) ? (trp - 1) : 0);
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outl(val, (dev ? &ftide020->dtrd1 : &ftide020->dtrd0));
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return 1;
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} else
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return 0;
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default:
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return 0;
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}
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}
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static void ftide_read_hwrev(void)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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unsigned int rev;
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rev = inl(&ftide020->revision);
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}
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static int ftide_controller_probe(void)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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unsigned int bak;
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bak = inl(&ftide020->ctrd1);
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/* probing by using shorter setup time */
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outl(CONFIG_CTRD1_PROBE_T1, &ftide020->ctrd1);
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if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T1) {
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outl(bak, &ftide020->ctrd1);
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return 0;
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}
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/* probing by using longer setup time */
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outl(CONFIG_CTRD1_PROBE_T2, &ftide020->ctrd1);
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if ((inl(&ftide020->ctrd1) & 0xff) != CONFIG_CTRD1_PROBE_T2) {
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outl(bak, &ftide020->ctrd1);
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return 0;
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}
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outl(bak, &ftide020->ctrd1);
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return 1;
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}
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/* ide_preinit() was migrated from linux driver ide_probe_for_ftide() */
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int ide_preinit(void)
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{
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static struct ftide020_s *ftide020 = (struct ftide020_s *) FTIDE_BASE;
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int status;
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unsigned int val;
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int i;
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status = 1;
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for (i = 0; i < CONFIG_SYS_IDE_MAXBUS; i++)
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ide_bus_offset[i] = -ATA_STATUS;
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/* auto-detect IDE controller */
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if (ftide_controller_probe()) {
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printf("FTIDE020_S\n");
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} else {
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printf("FTIDE020_S ATA controller not found.\n");
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return API_ENODEV;
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}
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/* check HW IP revision */
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ftide_read_hwrev();
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/* set FIFO threshold */
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outl(((WRITE_FIFO - RX_THRESH) << 16) | RX_THRESH, &ftide020->dmatirr);
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/* set Device_0 PIO_4 timing */
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set_mode_timing(0, CMD_TIMING, REG_MODE4);
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set_mode_timing(0, PIO_TIMING, PIO_MODE4);
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/* set Device_1 PIO_4 timing */
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set_mode_timing(1, CMD_TIMING, REG_MODE4);
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set_mode_timing(1, PIO_TIMING, PIO_MODE4);
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/* from E-bios */
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/* little endian */
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outl(0x0, &ftide020->cr);
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mdelay(10);
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outl(0x0fff0fff, &ftide020->ahbtr);
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mdelay(10);
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/* Enable controller Interrupt */
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val = inl(&ftide020->cr);
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/* Enable: IDE IRQ, IDE Terminate ERROR IRQ, AHB Timeout error IRQ */
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val |= (CONTROL_IIE | CONTROL_TERIE | CONTROL_AERIE);
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outl(val, &ftide020->cr);
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status = 0;
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return status;
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}
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void ide_set_reset(int flag)
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{
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debug("ide_set_reset()\n");
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reset_ide_controller();
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return;
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}
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