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![Michal Simek](/assets/img/avatar_default.png)
Do lowlevel initialization directly in C. Zynq do not require to do it in asm. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
86 lines
2.3 KiB
C
86 lines
2.3 KiB
C
/*
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* Copyright (c) 2013 Xilinx Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_ARCH_HARDWARE_H
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#define _ASM_ARCH_HARDWARE_H
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#define XPSS_SYS_CTRL_BASEADDR 0xF8000000
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#define XPSS_DEV_CFG_APB_BASEADDR 0xF8007000
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#define XPSS_SCU_BASEADDR 0xF8F00000
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/* Reflect slcr offsets */
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struct slcr_regs {
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u32 scl; /* 0x0 */
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u32 slcr_lock; /* 0x4 */
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u32 slcr_unlock; /* 0x8 */
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u32 reserved1[125];
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u32 pss_rst_ctrl; /* 0x200 */
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u32 reserved2[15];
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u32 fpga_rst_ctrl; /* 0x240 */
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u32 reserved3[5];
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u32 reboot_status; /* 0x258 */
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u32 boot_mode; /* 0x25c */
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u32 reserved4[116];
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u32 trust_zone; /* 0x430 */ /* FIXME */
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u32 reserved5[115];
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u32 ddr_urgent; /* 0x600 */
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u32 reserved6[6];
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u32 ddr_urgent_sel; /* 0x61c */
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u32 reserved7[188];
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u32 ocm_cfg; /* 0x910 */
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};
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#define slcr_base ((struct slcr_regs *) XPSS_SYS_CTRL_BASEADDR)
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struct devcfg_regs {
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u32 ctrl; /* 0x0 */
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u32 lock; /* 0x4 */
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u32 cfg; /* 0x8 */
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u32 int_sts; /* 0xc */
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u32 int_mask; /* 0x10 */
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u32 status; /* 0x14 */
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u32 dma_src_addr; /* 0x18 */
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u32 dma_dst_addr; /* 0x1c */
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u32 dma_src_len; /* 0x20 */
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u32 dma_dst_len; /* 0x24 */
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u32 rom_shadow; /* 0x28 */
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u32 reserved1[2];
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u32 unlock; /* 0x34 */
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u32 reserved2[18];
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u32 mctrl; /* 0x80 */
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u32 reserved3;
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u32 write_count; /* 0x88 */
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u32 read_count; /* 0x8c */
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};
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#define devcfg_base ((struct devcfg_regs *) XPSS_DEV_CFG_APB_BASEADDR)
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struct scu_regs {
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u32 reserved1[16];
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u32 filter_start; /* 0x40 */
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u32 filter_end; /* 0x44 */
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};
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#define scu_base ((struct scu_regs *) XPSS_SCU_BASEADDR)
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#endif /* _ASM_ARCH_HARDWARE_H */
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