mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 10:58:52 +09:00
150c24936b
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _UART_H_
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#define _UART_H_
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/* UART registers */
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struct uart_ctlr {
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uint uart_thr_dlab_0; /* UART_THR_DLAB_0_0, offset 00 */
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uint uart_ier_dlab_0; /* UART_IER_DLAB_0_0, offset 04 */
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uint uart_iir_fcr; /* UART_IIR_FCR_0, offset 08 */
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uint uart_lcr; /* UART_LCR_0, offset 0C */
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uint uart_mcr; /* UART_MCR_0, offset 10 */
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uint uart_lsr; /* UART_LSR_0, offset 14 */
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uint uart_msr; /* UART_MSR_0, offset 18 */
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uint uart_spr; /* UART_SPR_0, offset 1C */
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uint uart_irda_csr; /* UART_IRDA_CSR_0, offset 20 */
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uint uart_reserved[6]; /* Reserved, unused, offset 24-38*/
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uint uart_asr; /* UART_ASR_0, offset 3C */
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};
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#define NVRM_PLLP_FIXED_FREQ_KHZ 216000
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#define NV_DEFAULT_DEBUG_BAUD 115200
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#define UART_FCR_TRIGGER_3 0x30 /* Mask for trigger set at 3 */
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#endif /* UART_H */
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