mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 10:58:52 +09:00
150c24936b
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: Tom Warren <twarren@nvidia.com>
44 lines
1.6 KiB
C
44 lines
1.6 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SCU_H_
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#define _SCU_H_
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/* ARM Snoop Control Unit (SCU) registers */
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struct scu_ctlr {
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uint scu_ctrl; /* SCU Control Register, offset 00 */
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uint scu_cfg; /* SCU Config Register, offset 04 */
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uint scu_cpu_pwr_stat; /* SCU CPU Power Status Register, offset 08 */
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uint scu_inv_all; /* SCU Invalidate All Register, offset 0C */
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uint scu_reserved0[12]; /* reserved, offset 10-3C */
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uint scu_filt_start; /* SCU Filtering Start Address Reg, offset 40 */
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uint scu_filt_end; /* SCU Filtering End Address Reg, offset 44 */
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uint scu_reserved1[2]; /* reserved, offset 48-4C */
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uint scu_acc_ctl; /* SCU Access Control Register, offset 50 */
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uint scu_ns_acc_ctl; /* SCU Non-secure Access Cntrl Reg, offset 54 */
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};
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#define SCU_CTRL_ENABLE (1 << 0)
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#endif /* SCU_H */
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