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![Stefan Bosch](/assets/img/avatar_default.png)
Low level functions for MLC (Multi Layer Control) and MIPI (Mobile Industry Processor Interface). Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
581 lines
15 KiB
C
581 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Nexell Co., Ltd.
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*
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* Author: junghyun, kim <jhkim@nexell.co.kr>
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*/
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#include <linux/types.h>
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#include <linux/io.h>
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#include "s5pxx18_soc_disptop.h"
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#include "s5pxx18_soc_mipi.h"
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static struct nx_mipi_register_set *__g_pregister[NUMBER_OF_MIPI_MODULE];
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int nx_mipi_smoke_test(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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if (pregister->csis_config_ch0 != 0x000000FC)
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return false;
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if (pregister->dsim_intmsk != 0xB337FFFF)
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return false;
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writel(0xDEADC0DE, &pregister->csis_dphyctrl);
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writel(0xFFFFFFFF, &pregister->csis_ctrl2);
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writel(0xDEADC0DE, &pregister->dsim_msync);
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if (pregister->csis_dphyctrl != 0xDE80001E)
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return false;
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if ((pregister->csis_ctrl2 & (~1)) != 0xEEE00010)
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return false;
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if (pregister->dsim_msync != 0xDE80C0DE)
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return false;
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return true;
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}
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void nx_mipi_set_base_address(u32 module_index, void *base_address)
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{
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__g_pregister[module_index] =
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(struct nx_mipi_register_set *)base_address;
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}
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void *nx_mipi_get_base_address(u32 module_index)
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{
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return (void *)__g_pregister[module_index];
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}
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u32 nx_mipi_get_physical_address(u32 module_index)
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{
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const u32 physical_addr[] = PHY_BASEADDR_MIPI_LIST;
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return physical_addr[module_index];
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}
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#define __nx_mipi_valid_dsi_intmask__ \
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(~((1 << 26) | (1 << 23) | (1 << 22) | (1 << 19)))
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void nx_mipi_set_interrupt_enable(u32 module_index, u32 int_num, int enable)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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if (int_num < 32) {
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regvalue = pregister->csis_intmsk;
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regvalue &= ~(1ul << int_num);
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regvalue |= (u32)enable << int_num;
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writel(regvalue, &pregister->csis_intmsk);
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} else {
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regvalue = pregister->dsim_intmsk;
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regvalue &= ~(1ul << (int_num - 32));
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regvalue |= (u32)enable << (int_num - 32);
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writel(regvalue, &pregister->dsim_intmsk);
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}
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}
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int nx_mipi_get_interrupt_enable(u32 module_index, u32 int_num)
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{
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if (int_num < 32)
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return (int)((__g_pregister[module_index]->csis_intmsk >>
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int_num) & 0x01);
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else
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return (int)((__g_pregister[module_index]->dsim_intmsk >>
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(int_num - 32)) & 0x01);
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}
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int nx_mipi_get_interrupt_pending(u32 module_index, u32 int_num)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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int ret;
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pregister = __g_pregister[module_index];
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if (int_num < 32) {
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regvalue = pregister->csis_intmsk;
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regvalue &= pregister->csis_intsrc;
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ret = (int)((regvalue >> int_num) & 0x01);
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} else {
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regvalue = pregister->dsim_intmsk;
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regvalue &= pregister->dsim_intsrc;
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ret = (int)((regvalue >> (int_num - 32)) & 0x01);
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}
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return ret;
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}
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void nx_mipi_clear_interrupt_pending(u32 module_index, u32 int_num)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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if (int_num < 32)
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writel(1ul << int_num, &pregister->csis_intsrc);
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else
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writel(1ul << (int_num - 32), &pregister->dsim_intsrc);
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}
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void nx_mipi_set_interrupt_enable_all(u32 module_index, int enable)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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if (enable)
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writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intmsk);
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else
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writel(0, &pregister->dsim_intmsk);
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}
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int nx_mipi_get_interrupt_enable_all(u32 module_index)
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{
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if (__g_pregister[module_index]->csis_intmsk)
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return true;
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if (__g_pregister[module_index]->dsim_intmsk)
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return true;
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return false;
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}
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int nx_mipi_get_interrupt_pending_all(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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regvalue = pregister->csis_intmsk;
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regvalue &= pregister->csis_intsrc;
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if (regvalue)
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return true;
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regvalue = pregister->dsim_intmsk;
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regvalue &= pregister->dsim_intsrc;
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if (regvalue)
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return true;
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return false;
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}
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void nx_mipi_clear_interrupt_pending_all(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intsrc);
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}
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int32_t nx_mipi_get_interrupt_pending_number(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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int i;
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pregister = __g_pregister[module_index];
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regvalue = pregister->csis_intmsk;
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regvalue &= pregister->csis_intsrc;
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if (regvalue != 0) {
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for (i = 0; i < 32; i++) {
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if (regvalue & 1ul)
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return i;
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regvalue >>= 1;
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}
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}
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regvalue = pregister->dsim_intmsk;
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regvalue &= pregister->dsim_intsrc;
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if (regvalue != 0) {
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for (i = 0; i < 32; i++) {
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if (regvalue & 1ul)
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return i + 32;
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regvalue >>= 1;
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}
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}
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return -1;
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}
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#define writereg(regname, mask, value) \
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regvalue = pregister->(regname); \
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regvalue = (regvalue & (~(mask))) | (value); \
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writel(regvalue, &pregister->(regname))
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void nx_mipi_dsi_get_status(u32 module_index, u32 *pulps, u32 *pstop,
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u32 *pispllstable, u32 *pisinreset,
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u32 *pisbackward, u32 *pishsclockready)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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regvalue = pregister->dsim_status;
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if (pulps) {
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*pulps = 0;
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if (regvalue & (1 << 4))
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*pulps |= (1 << 0);
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if (regvalue & (1 << 5))
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*pulps |= (1 << 1);
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if (regvalue & (1 << 6))
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*pulps |= (1 << 2);
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if (regvalue & (1 << 7))
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*pulps |= (1 << 3);
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if (regvalue & (1 << 9))
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*pulps |= (1 << 4);
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}
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if (pstop) {
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*pstop = 0;
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if (regvalue & (1 << 0))
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*pstop |= (1 << 0);
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if (regvalue & (1 << 1))
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*pstop |= (1 << 1);
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if (regvalue & (1 << 2))
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*pstop |= (1 << 2);
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if (regvalue & (1 << 3))
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*pstop |= (1 << 3);
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if (regvalue & (1 << 8))
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*pstop |= (1 << 4);
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}
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if (pispllstable)
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*pispllstable = (regvalue >> 31) & 1;
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if (pisinreset)
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*pisinreset = ((regvalue >> 20) & 1) ? 0 : 1;
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if (pisbackward)
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*pisbackward = (regvalue >> 16) & 1;
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if (pishsclockready)
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*pishsclockready = (regvalue >> 10) & 1;
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}
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void nx_mipi_dsi_software_reset(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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writel(0x00010001, &pregister->dsim_swrst);
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while (0 != (readl(&pregister->dsim_status) & (1 << 20)))
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;
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writel(0x00000000, &pregister->dsim_swrst);
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}
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void nx_mipi_dsi_set_clock(u32 module_index, int enable_txhsclock,
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int use_external_clock, int enable_byte_clock,
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int enable_escclock_clock_lane,
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int enable_escclock_data_lane0,
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int enable_escclock_data_lane1,
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int enable_escclock_data_lane2,
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int enable_escclock_data_lane3,
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int enable_escprescaler, u32 escprescalervalue)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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regvalue = 0;
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regvalue |= (enable_txhsclock << 31);
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regvalue |= (use_external_clock << 27);
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regvalue |= (enable_byte_clock << 24);
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regvalue |= (enable_escclock_clock_lane << 19);
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regvalue |= (enable_escclock_data_lane0 << 20);
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regvalue |= (enable_escclock_data_lane1 << 21);
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regvalue |= (enable_escclock_data_lane2 << 22);
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regvalue |= (enable_escclock_data_lane3 << 23);
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regvalue |= (enable_escprescaler << 28);
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regvalue |= escprescalervalue;
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writel(regvalue, &pregister->dsim_clkctrl);
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}
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void nx_mipi_dsi_set_timeout(u32 module_index, u32 bta_tout, u32 lpdrtout)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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regvalue = 0;
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regvalue |= (bta_tout << 16);
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regvalue |= (lpdrtout << 0);
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writel(regvalue, &pregister->dsim_timeout);
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}
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void nx_mipi_dsi_set_config_video_mode(u32 module_index,
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int enable_auto_flush_main_display_fifo,
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int enable_auto_vertical_count,
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int enable_burst,
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enum nx_mipi_dsi_syncmode sync_mode,
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int enable_eo_tpacket,
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int enable_hsync_end_packet,
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int enable_hfp, int enable_hbp,
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int enable_hsa,
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u32 number_of_virtual_channel,
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enum nx_mipi_dsi_format format,
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u32 number_of_words_in_hfp,
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u32 number_of_words_in_hbp,
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u32 number_of_words_in_hsync,
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u32 number_of_lines_in_vfp,
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u32 number_of_lines_in_vbp,
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u32 number_of_lines_in_vsync,
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u32 number_of_lines_in_command_allow)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (1 << 25);
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newvalue |= ((1 - enable_auto_flush_main_display_fifo) << 29);
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newvalue |= (enable_auto_vertical_count << 24);
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newvalue |= (enable_burst << 26);
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newvalue |= (sync_mode << 27);
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newvalue |= ((1 - enable_eo_tpacket) << 28);
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newvalue |= (enable_hsync_end_packet << 23);
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newvalue |= ((1 - enable_hfp) << 22);
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newvalue |= ((1 - enable_hbp) << 21);
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newvalue |= ((1 - enable_hsa) << 20);
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newvalue |= (number_of_virtual_channel << 18);
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newvalue |= (format << 12);
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writereg(dsim_config, 0xFFFFFF00, newvalue);
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newvalue = (number_of_lines_in_command_allow << 28);
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newvalue |= (number_of_lines_in_vfp << 16);
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newvalue |= (number_of_lines_in_vbp << 0);
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writel(newvalue, &pregister->dsim_mvporch);
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newvalue = (number_of_words_in_hfp << 16);
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newvalue |= (number_of_words_in_hbp << 0);
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writel(newvalue, &pregister->dsim_mhporch);
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newvalue = (number_of_words_in_hsync << 0);
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newvalue |= (number_of_lines_in_vsync << 22);
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writel(newvalue, &pregister->dsim_msync);
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}
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void nx_mipi_dsi_set_config_command_mode(u32 module_index,
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int
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enable_auto_flush_main_display_fifo,
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int enable_eo_tpacket,
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u32 number_of_virtual_channel,
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enum nx_mipi_dsi_format format)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (0 << 25);
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newvalue |= (enable_auto_flush_main_display_fifo << 29);
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newvalue |= (enable_eo_tpacket << 28);
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newvalue |= (number_of_virtual_channel << 18);
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newvalue |= (format << 12);
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writereg(dsim_config, 0xFFFFFF00, newvalue);
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}
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void nx_mipi_dsi_set_escape_mode(u32 module_index, u32 stop_state_count,
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int force_stop_state, int force_bta,
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enum nx_mipi_dsi_lpmode cmdin_lp,
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enum nx_mipi_dsi_lpmode txinlp)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (stop_state_count << 21);
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newvalue |= (force_stop_state << 20);
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newvalue |= (force_bta << 16);
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newvalue |= (cmdin_lp << 7);
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newvalue |= (txinlp << 6);
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writereg(dsim_escmode, 0xFFFFFFC0, newvalue);
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}
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void nx_mipi_dsi_set_escape_lp(u32 module_index,
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enum nx_mipi_dsi_lpmode cmdin_lp,
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enum nx_mipi_dsi_lpmode txinlp)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue = 0;
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pregister = __g_pregister[module_index];
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newvalue |= (cmdin_lp << 7);
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newvalue |= (txinlp << 6);
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writereg(dsim_escmode, 0xC0, newvalue);
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}
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void nx_mipi_dsi_remote_reset_trigger(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (1 << 4);
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writereg(dsim_escmode, (1 << 4), newvalue);
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while (readl(&pregister->dsim_escmode) & (1 << 4))
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;
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}
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void nx_mipi_dsi_set_ulps(u32 module_index, int ulpsclocklane, int ulpsdatalane)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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regvalue = pregister->dsim_escmode;
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if (ulpsclocklane) {
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regvalue &= ~(1 << 0);
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regvalue |= (1 << 1);
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} else {
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regvalue |= (1 << 0);
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}
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if (ulpsdatalane) {
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regvalue &= ~(1 << 2);
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regvalue |= (1 << 3);
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} else {
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regvalue |= (1 << 2);
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}
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writel(regvalue, &pregister->dsim_escmode);
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if (ulpsclocklane)
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while ((1 << 9) ==
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(readl(&pregister->dsim_status) & (1 << 9)))
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;
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else
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while (0 != (readl(&pregister->dsim_status) & (1 << 9)))
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;
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if (ulpsdatalane)
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while ((15 << 4) ==
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(readl(&pregister->dsim_status) & (15 << 4)))
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;
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else
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while (0 != (readl(&pregister->dsim_status) & (15 << 4)))
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;
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if (!ulpsclocklane)
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regvalue &= (3 << 0);
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if (!ulpsdatalane)
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regvalue |= (3 << 2);
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writel(regvalue, &pregister->dsim_escmode);
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}
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void nx_mipi_dsi_set_size(u32 module_index, u32 width, u32 height)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (height << 16);
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newvalue |= (width << 0);
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writereg(dsim_mdresol, 0x0FFFFFFF, newvalue);
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}
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void nx_mipi_dsi_set_enable(u32 module_index, int enable)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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pregister = __g_pregister[module_index];
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writereg(dsim_mdresol, (1 << 31), (enable << 31));
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}
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void nx_mipi_dsi_set_phy(u32 module_index, u32 number_of_data_lanes,
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int enable_clock_lane, int enable_data_lane0,
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int enable_data_lane1, int enable_data_lane2,
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int enable_data_lane3, int swap_clock_lane,
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int swap_data_lane)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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newvalue = (number_of_data_lanes << 5);
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newvalue |= (enable_clock_lane << 0);
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newvalue |= (enable_data_lane0 << 1);
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newvalue |= (enable_data_lane1 << 2);
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newvalue |= (enable_data_lane2 << 3);
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newvalue |= (enable_data_lane3 << 4);
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writereg(dsim_config, 0xFF, newvalue);
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newvalue = (swap_clock_lane << 1);
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newvalue |= (swap_data_lane << 0);
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writereg(dsim_phyacchr1, 0x3, newvalue);
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}
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void nx_mipi_dsi_set_pll(u32 module_index, int enable, u32 pllstabletimer,
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u32 m_pllpms, u32 m_bandctl, u32 m_dphyctl,
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u32 b_dphyctl)
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{
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register struct nx_mipi_register_set *pregister;
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register u32 regvalue;
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u32 newvalue;
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pregister = __g_pregister[module_index];
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if (!enable) {
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newvalue = (enable << 23);
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newvalue |= (m_pllpms << 1);
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newvalue |= (m_bandctl << 24);
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writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue);
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}
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writel(m_dphyctl, &pregister->dsim_phyacchr);
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writel(pllstabletimer, &pregister->dsim_plltmr);
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writel((b_dphyctl << 9), &pregister->dsim_phyacchr1);
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if (enable) {
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newvalue = (enable << 23);
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newvalue |= (m_pllpms << 1);
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newvalue |= (m_bandctl << 24);
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writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue);
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}
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}
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void nx_mipi_dsi_write_pkheader(u32 module_index, u32 data)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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writel(data, &pregister->dsim_pkthdr);
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}
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void nx_mipi_dsi_write_payload(u32 module_index, u32 data)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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writel(data, &pregister->dsim_payload);
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}
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u32 nx_mipi_dsi_read_fifo_status(u32 module_index)
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{
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register struct nx_mipi_register_set *pregister;
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pregister = __g_pregister[module_index];
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return readl(&pregister->dsim_fifoctrl);
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}
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