Marek Vasut 8f975865be i.MX28: Add delay after CPU bypass is cleared ... This solves issues when larger amount of DRAM is used, like 256MB. Behave the same in case of CPU bypass as we do in case of EMI bypass, but wait 15 ms. We need to wait until the clock domain stabilizes. This issue seemed to have been caused by not waiting after frobbing with the CPU bypass, it was unrelated to memory, but had a direct impact, causing trouble. This was yet another X-File of the imx-bootlets, sigh. The conclusion is, trying a semi-random delay (there is delay after the EMI bypass change), the issue is fixed. Another possible explanation is that we do not do the "simple memory test" FSL does in their imx-bootlets (1000 R/W cycles to/from piece of the memory, while also outputing something on the serial port). This might have caused the similar delay in the imx-bootlets and therefore they didn't need to add this explicitly. For now, this seems good fix enough, but to me, whole that memory init code in imx-bootlets is completely flunked and it'd need deeper investigation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> Acked-by: Detlev Zundel <dzu@denx.de>		2012-05-15 08:31:35 +02:00
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cpu	i.MX28: Add delay after CPU bypass is cleared	2012-05-15 08:31:35 +02:00
dts	tegra: fdt: i2c: Add extra I2C bindings for U-Boot	2012-03-29 08:12:50 +02:00
include/asm	mx53loco: Add CONFIG_REVISION_TAG	2012-05-15 08:31:34 +02:00
lib	arm: restore fdt_fixup_ethernet call to do_bootm_linux	2012-04-23 22:11:18 +02:00
config.mk	Makefile: Add a 'checkthumb' rule	2012-05-15 08:31:26 +02:00