mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
7f52ed5ef1
eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
279 lines
8.0 KiB
C
279 lines
8.0 KiB
C
/*
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* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao, (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ppc_asm.tmpl>
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#include <asm/processor.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* --------------------------------------------------------------- */
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void get_sys_info (sys_info_t * sysInfo)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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#ifdef CONFIG_FSL_CORENET
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volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
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const u8 core_cplx_PLL[16] = {
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[ 0] = 0, /* CC1 PPL / 1 */
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[ 1] = 0, /* CC1 PPL / 2 */
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[ 2] = 0, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 1, /* CC2 PPL / 2 */
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[ 6] = 1, /* CC2 PPL / 4 */
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[ 8] = 2, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 2, /* CC3 PPL / 4 */
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[12] = 3, /* CC4 PPL / 1 */
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[13] = 3, /* CC4 PPL / 2 */
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[14] = 3, /* CC4 PPL / 4 */
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};
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const u8 core_cplx_PLL_div[16] = {
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[ 0] = 1, /* CC1 PPL / 1 */
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[ 1] = 2, /* CC1 PPL / 2 */
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[ 2] = 4, /* CC1 PPL / 4 */
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[ 4] = 1, /* CC2 PPL / 1 */
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[ 5] = 2, /* CC2 PPL / 2 */
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[ 6] = 4, /* CC2 PPL / 4 */
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[ 8] = 1, /* CC3 PPL / 1 */
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[ 9] = 2, /* CC3 PPL / 2 */
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[10] = 4, /* CC3 PPL / 4 */
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[12] = 1, /* CC4 PPL / 1 */
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[13] = 2, /* CC4 PPL / 2 */
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[14] = 4, /* CC4 PPL / 4 */
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};
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uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
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unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
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sysInfo->freqSystemBus = sysclk;
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sysInfo->freqDDRBus = sysclk;
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freqCC_PLL[0] = sysclk;
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freqCC_PLL[1] = sysclk;
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freqCC_PLL[2] = sysclk;
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freqCC_PLL[3] = sysclk;
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sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0xf;
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sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0xf);
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freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
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freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
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freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
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freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
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rcw_tmp = in_be32(&gur->rcwsr[3]);
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for (i = 0; i < cpu_numcores(); i++) {
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u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;
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u32 cplx_pll = core_cplx_PLL[c_pll_sel];
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sysInfo->freqProcessor[i] =
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freqCC_PLL[cplx_pll] / core_cplx_PLL_div[c_pll_sel];
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}
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#define PME_CLK_SEL 0x80000000
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#define FM1_CLK_SEL 0x40000000
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#define FM2_CLK_SEL 0x20000000
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rcw_tmp = in_be32(&gur->rcwsr[7]);
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#ifdef CONFIG_SYS_DPAA_PME
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if (rcw_tmp & PME_CLK_SEL)
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sysInfo->freqPME = freqCC_PLL[2] / 2;
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else
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sysInfo->freqPME = sysInfo->freqSystemBus / 2;
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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if (rcw_tmp & FM1_CLK_SEL)
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sysInfo->freqFMan[0] = freqCC_PLL[2] / 2;
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else
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sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2;
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#if (CONFIG_SYS_NUM_FMAN) == 2
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if (rcw_tmp & FM2_CLK_SEL)
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sysInfo->freqFMan[1] = freqCC_PLL[2] / 2;
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else
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sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2;
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#endif
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#endif
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#else
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uint plat_ratio,e500_ratio,half_freqSystemBus;
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uint lcrr_div;
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int i;
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#ifdef CONFIG_QE
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u32 qe_ratio;
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#endif
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plat_ratio = (gur->porpllsr) & 0x0000003e;
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plat_ratio >>= 1;
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sysInfo->freqSystemBus = plat_ratio * CONFIG_SYS_CLK_FREQ;
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/* Divide before multiply to avoid integer
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* overflow for processor speeds above 2GHz */
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half_freqSystemBus = sysInfo->freqSystemBus/2;
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for (i = 0; i < cpu_numcores(); i++) {
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e500_ratio = ((gur->porpllsr) >> (i * 8 + 16)) & 0x3f;
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sysInfo->freqProcessor[i] = e500_ratio * half_freqSystemBus;
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}
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/* Note: freqDDRBus is the MCLK frequency, not the data rate. */
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sysInfo->freqDDRBus = sysInfo->freqSystemBus;
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#ifdef CONFIG_DDR_CLK_FREQ
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{
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u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
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>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
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if (ddr_ratio != 0x7)
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sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
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}
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#endif
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#endif
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#ifdef CONFIG_QE
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qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
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>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
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sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
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#endif
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#if defined(CONFIG_SYS_LBC_LCRR)
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/* We will program LCRR to this value later */
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lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
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#else
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{
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volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
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}
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#endif
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if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
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#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && \
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!defined(CONFIG_MPC8555) && !defined(CONFIG_MPC8560)
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/*
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* Yes, the entire PQ38 family use the same
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* bit-representation for twice the clock divider values.
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*/
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lcrr_div *= 2;
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#endif
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sysInfo->freqLocalBus = sysInfo->freqSystemBus / lcrr_div;
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} else {
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/* In case anyone cares what the unknown value is */
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sysInfo->freqLocalBus = lcrr_div;
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}
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}
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int get_clocks (void)
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{
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sys_info_t sys_info;
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#ifdef CONFIG_MPC8544
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volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR;
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#endif
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#if defined(CONFIG_CPM2)
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volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
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uint sccr, dfbrg;
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/* set VCO = 4 * BRG */
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cpm->im_cpm_intctl.sccr &= 0xfffffffc;
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sccr = cpm->im_cpm_intctl.sccr;
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dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
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#endif
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get_sys_info (&sys_info);
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gd->cpu_clk = sys_info.freqProcessor[0];
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gd->bus_clk = sys_info.freqSystemBus;
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gd->mem_clk = sys_info.freqDDRBus;
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gd->lbc_clk = sys_info.freqLocalBus;
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#ifdef CONFIG_QE
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gd->qe_clk = sys_info.freqQE;
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gd->brg_clk = gd->qe_clk / 2;
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#endif
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/*
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* The base clock for I2C depends on the actual SOC. Unfortunately,
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* there is no pattern that can be used to determine the frequency, so
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* the only choice is to look up the actual SOC number and use the value
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* for that SOC. This information is taken from application note
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* AN2919.
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*/
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#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \
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defined(CONFIG_MPC8560) || defined(CONFIG_MPC8555)
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gd->i2c1_clk = sys_info.freqSystemBus;
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#elif defined(CONFIG_MPC8544)
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/*
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* On the 8544, the I2C clock is the same as the SEC clock. This can be
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* either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See
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* 4.4.3.3 of the 8544 RM. Note that this might actually work for all
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* 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the
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* PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544.
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*/
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if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG)
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gd->i2c1_clk = sys_info.freqSystemBus / 3;
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else
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#else
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/* Most 85xx SOCs use CCB/2, so this is the default behavior. */
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gd->i2c1_clk = sys_info.freqSystemBus / 2;
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#endif
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gd->i2c2_clk = gd->i2c1_clk;
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#if defined(CONFIG_FSL_ESDHC)
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#ifdef CONFIG_MPC8569
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gd->sdhc_clk = gd->bus_clk;
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#else
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gd->sdhc_clk = gd->bus_clk / 2;
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#endif
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#endif /* defined(CONFIG_FSL_ESDHC) */
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#if defined(CONFIG_CPM2)
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gd->vco_out = 2*sys_info.freqSystemBus;
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gd->cpm_clk = gd->vco_out / 2;
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gd->scc_clk = gd->vco_out / 4;
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gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
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#endif
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if(gd->cpu_clk != 0) return (0);
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else return (1);
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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return gd->bus_clk;
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}
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/********************************************
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq (ulong dummy)
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{
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return gd->mem_clk;
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}
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