Chris Zankel de5e5cea02 xtensa: add support for the xtensa processor architecture [1/2] ... The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Cadence. This is the first part of the basic architecture port with changes to common files. The 'arch/xtensa' directory, and boards and additional drivers will be in separate commits. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>		2016-08-15 18:46:38 -04:00
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byteorder
mtd	mtd: fix compiler warnings	2016-07-24 20:36:29 -05:00
unaligned
usb	include: usb: Rename USB controller base address mapping	2016-07-26 09:01:04 -07:00
apm_bios.h
bch.h
bitops.h
bitrev.h
bug.h
compat.h
compiler-clang.h
compiler-gcc.h
compiler-intel.h
compiler.h
crc7.h
crc8.h
crc32.h
ctype.h
drm_dp_helper.h
edd.h
err.h
ethtool.h
fb.h
immap_qe.h
input.h
io.h
ioctl.h
ioport.h
kbuild.h
kconfig.h
kernel.h
linkage.h
linux_string.h
list_sort.h
list.h
log2.h
lzo.h
math64.h
mbus.h
mc146818rtc.h
mdio.h
mii.h
netdevice.h
poison.h
posix_types.h
psci.h
rbtree_augmented.h
rbtree.h
screen_info.h
serial_reg.h
sizes.h
stat.h	xtensa: add support for the xtensa processor architecture [1/2]	2016-08-15 18:46:38 -04:00
stddef.h
string.h
stringify.h
time.h
types.h