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![Peng Fan](/assets/img/avatar_default.png)
Introduce io_gate_val for sandbox clk gate test usage Signed-off-by: Peng Fan <peng.fan@nxp.com>
160 lines
3.4 KiB
C
160 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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* Copyright 2019 NXP
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*
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* Gated clock implementation
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <clk-uclass.h>
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#include <dm/device.h>
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#include <linux/clk-provider.h>
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#include <clk.h>
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#include "clk.h"
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#define UBOOT_DM_CLK_GATE "clk_gate"
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/**
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* DOC: basic gatable clock which can gate and ungate it's output
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parent is (un)prepared
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* enable - clk_enable and clk_disable are functional & control gating
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* rate - inherits rate from parent. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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/*
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* It works on following logic:
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*
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* For enabling clock, enable = 1
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* set2dis = 1 -> clear bit -> set = 0
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* set2dis = 0 -> set bit -> set = 1
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*
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* For disabling clock, enable = 0
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* set2dis = 1 -> set bit -> set = 1
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* set2dis = 0 -> clear bit -> set = 0
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*
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* So, result is always: enable xor set2dis.
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*/
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static void clk_gate_endisable(struct clk *clk, int enable)
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{
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struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
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u32 reg;
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set ^= enable;
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if (gate->flags & CLK_GATE_HIWORD_MASK) {
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reg = BIT(gate->bit_idx + 16);
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if (set)
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reg |= BIT(gate->bit_idx);
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} else {
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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reg = gate->io_gate_val;
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#else
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reg = readl(gate->reg);
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#endif
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if (set)
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reg |= BIT(gate->bit_idx);
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else
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reg &= ~BIT(gate->bit_idx);
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}
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writel(reg, gate->reg);
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}
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static int clk_gate_enable(struct clk *clk)
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{
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clk_gate_endisable(clk, 1);
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return 0;
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}
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static int clk_gate_disable(struct clk *clk)
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{
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clk_gate_endisable(clk, 0);
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return 0;
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}
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int clk_gate_is_enabled(struct clk *clk)
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{
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struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
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dev_get_clk_ptr(clk->dev) : clk);
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u32 reg;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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reg = gate->io_gate_val;
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#else
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reg = readl(gate->reg);
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#endif
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/* if a set bit disables this clk, flip it before masking */
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if (gate->flags & CLK_GATE_SET_TO_DISABLE)
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reg ^= BIT(gate->bit_idx);
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reg &= BIT(gate->bit_idx);
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return reg ? 1 : 0;
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}
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const struct clk_ops clk_gate_ops = {
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.enable = clk_gate_enable,
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.disable = clk_gate_disable,
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.get_rate = clk_generic_get_rate,
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};
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struct clk *clk_register_gate(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock)
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{
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struct clk_gate *gate;
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struct clk *clk;
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int ret;
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if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
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if (bit_idx > 15) {
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pr_err("gate bit exceeds LOWORD field\n");
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return ERR_PTR(-EINVAL);
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}
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}
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/* allocate the gate */
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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/* struct clk_gate assignments */
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gate->reg = reg;
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gate->bit_idx = bit_idx;
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gate->flags = clk_gate_flags;
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#if CONFIG_IS_ENABLED(SANDBOX_CLK_CCF)
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gate->io_gate_val = *(u32 *)reg;
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#endif
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clk = &gate->clk;
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ret = clk_register(clk, UBOOT_DM_CLK_GATE, name, parent_name);
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if (ret) {
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kfree(gate);
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return ERR_PTR(ret);
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}
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return clk;
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}
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U_BOOT_DRIVER(clk_gate) = {
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.name = UBOOT_DM_CLK_GATE,
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.id = UCLASS_CLK,
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.ops = &clk_gate_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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