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![]() DESCRIPTION: The column address width settings for banks 2 and 3 are misconnected in the SDRAM controller. Accesses to bank 2 will result in an error if the Column Address Width for bank 3 (EB3CAW ) is not set to be the same as that of bank 2. WORKAROUND: If using bank 2, make sure that banks 2 and 3 have the same column address width settings in the EBIU_SDBCTL register. This must be the case regardless of whether or not bank 3 is enabled. Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
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.. | ||
.gitignore | ||
bootrom-asm-offsets.awk | ||
bootrom-asm-offsets.c.in | ||
cache.S | ||
cpu.c | ||
cpu.h | ||
initcode.c | ||
interrupt.S | ||
interrupts.c | ||
jtag-console.c | ||
Makefile | ||
reset.c | ||
serial.c | ||
serial.h | ||
start.S | ||
system_map.S | ||
traps.c | ||
watchdog.c |