mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 15:46:16 +09:00
8ef07571a0
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_CAR_ADDR 0xff7e0000
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#define CONFIG_SYS_CAR_SIZE (128 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_NR_DRAM_BANKS 8
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#define CONFIG_COREBOOT_SERIAL
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#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
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{PCI_VENDOR_ID_INTEL, \
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PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
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/*
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* These common x86 features are not yet supported, but are added in
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* follow-on patches in this series. Add undefs here to avoid every patch
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* having to put things back into x86-common.h
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*/
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#undef CONFIG_INTEL_ICH6_GPIO
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#undef CONFIG_DM_GPIO
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#undef CONFIG_CMD_GPIO
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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#undef CONFIG_SYS_EARLY_PCI_INIT
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#undef CONFIG_PCI
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#undef CONFIG_ICH_SPI
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#undef CONFIG_SPI
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#undef CONFIG_CMD_SPI
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#undef CONFIG_CMD_SF
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#undef CONFIG_USB_EHCI
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#undef CONFIG_CMD_USB
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#undef CONFIG_CMD_SCSI
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
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"stdout=vga,serial\0" \
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"stderr=vga,serial\0"
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#endif /* __CONFIG_H */
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