mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-30 08:30:50 +09:00
8ef07571a0
This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org>
44 lines
1.2 KiB
Plaintext
44 lines
1.2 KiB
Plaintext
menu "x86 architecture"
|
|
depends on X86
|
|
|
|
config SYS_ARCH
|
|
default "x86"
|
|
|
|
config USE_PRIVATE_LIBGCC
|
|
default y
|
|
|
|
choice
|
|
prompt "Target select"
|
|
|
|
config TARGET_COREBOOT
|
|
bool "Support coreboot"
|
|
help
|
|
This target is used for running U-Boot on top of Coreboot. In
|
|
this case Coreboot does the early inititalisation, and U-Boot
|
|
takes over once the RAM, video and CPU are fully running.
|
|
U-Boot is loaded as a fallback payload from Coreboot, in
|
|
Coreboot terminology. This method was used for the Chromebook
|
|
Pixel when launched.
|
|
|
|
config TARGET_CHROMEBOOK_LINK
|
|
bool "Support Chromebook link"
|
|
help
|
|
This is the Chromebook Pixel released in 2013. It uses an Intel
|
|
i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
|
|
SDRAM. It has a Panther Point platform controller hub, PCIe
|
|
WiFi and Bluetooth. It also includes a 720p webcam, USB SD
|
|
reader, microphone and speakers, display port and 32GB SATA
|
|
solid state drive. There is a Chrome OS EC connected on LPC,
|
|
and it provides a 2560x1700 high resolution touch-enabled LCD
|
|
display.
|
|
|
|
endchoice
|
|
|
|
source "arch/x86/cpu/ivybridge/Kconfig"
|
|
|
|
source "board/chromebook-x86/coreboot/Kconfig"
|
|
|
|
source "board/google/chromebook_link/Kconfig"
|
|
|
|
endmenu
|