mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 12:59:43 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
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#include <../serdes/a38x/high_speed_env_spec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ETH_PHY_CTRL_REG 0
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#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
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#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
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/*
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-15t1-clearfog"
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*/
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#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
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#define BOARD_GPP_OUT_ENA_MID 0xffffffff
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#define BOARD_GPP_OUT_VAL_LOW 0x0
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#define BOARD_GPP_OUT_VAL_MID 0x0
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#define BOARD_GPP_POL_LOW 0x0
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#define BOARD_GPP_POL_MID 0x0
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/* IO expander on Marvell GP board includes e.g. fan enabling */
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struct marvell_io_exp {
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u8 chip;
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u8 addr;
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u8 val;
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};
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static struct marvell_io_exp io_exp[] = {
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{ 0x20, 2, 0x40 }, /* Deassert both mini pcie reset signals */
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{ 0x20, 6, 0xf9 },
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{ 0x20, 2, 0x46 }, /* rst signals and ena USB3 current limiter */
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{ 0x20, 6, 0xb9 },
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{ 0x20, 3, 0x00 }, /* Set SFP_TX_DIS to zero */
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{ 0x20, 7, 0xbf }, /* Drive SFP_TX_DIS to zero */
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};
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static struct serdes_map board_serdes_map[] = {
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{SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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{PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
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{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
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};
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int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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{
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*serdes_map_array = board_serdes_map;
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*count = ARRAY_SIZE(board_serdes_map);
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return 0;
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}
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/*
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* Define the DDR layout / topology here in the board file. This will
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* be used by the DDR3 init code in the SPL U-Boot version to configure
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* the DDR3 controller.
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*/
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static struct hws_topology_map board_topology_map = {
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
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{ { { {0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0},
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{0x1, 0, 0, 0} },
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SPEED_BIN_DDR_1600K, /* speed_bin */
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BUS_WIDTH_16, /* memory_width */
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MEM_4G, /* mem_size */
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DDR_FREQ_800, /* frequency */
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0, 0, /* cas_wl cas_l */
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HWS_TEMP_LOW, /* temperature */
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HWS_TIM_DEFAULT} }, /* timing */
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5, /* Num Of Bus Per Interface*/
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BUS_MASK_32BIT /* Busses mask */
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};
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struct hws_topology_map *ddr3_get_topology_map(void)
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{
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/* Return the board topology as defined in the board code */
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return &board_topology_map;
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}
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int board_early_init_f(void)
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{
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/* Configure MPP */
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writel(0x11111111, MVEBU_MPP_BASE + 0x00);
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writel(0x11111111, MVEBU_MPP_BASE + 0x04);
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writel(0x10400011, MVEBU_MPP_BASE + 0x08);
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writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
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writel(0x44400002, MVEBU_MPP_BASE + 0x10);
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writel(0x41144004, MVEBU_MPP_BASE + 0x14);
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writel(0x40333333, MVEBU_MPP_BASE + 0x18);
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writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
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/* Set GPP Out value */
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writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
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writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
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/* Set GPP Polarity */
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writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
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writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
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/* Set GPP Out Enable */
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writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
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writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
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return 0;
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}
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int board_init(void)
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{
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int i;
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/* Address of boot parameters */
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gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
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/* Toggle GPIO41 to reset onboard switch and phy */
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clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
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/* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
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clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
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mdelay(1);
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setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
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setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
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mdelay(10);
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/* Init I2C IO expanders */
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for (i = 0; i < ARRAY_SIZE(io_exp); i++)
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i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: SolidRun ClearFog\n");
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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cpu_eth_init(bis); /* Built in controller(s) come first */
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return pci_eth_init(bis);
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}
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