mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-26 21:03:44 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
112 lines
3.6 KiB
INI
112 lines
3.6 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* Copyright (C) 2017 Logic PD, Inc.
|
|
* Adam Ford <aford173@gmail.com>
|
|
*
|
|
* Refer doc/README.imximage for more details about how-to configure
|
|
* and create imximage boot image
|
|
*
|
|
* The syntax is taken as close as possible with the kwbimage
|
|
*/
|
|
|
|
#include <asm/mach-imx/imximage.cfg>
|
|
|
|
/* image version */
|
|
IMAGE_VERSION 2
|
|
|
|
BOOT_OFFSET FLASH_OFFSET_STANDARD
|
|
|
|
/*
|
|
* Device Configuration Data (DCD)
|
|
*
|
|
* Each entry must have the format:
|
|
* Addr-type Address Value
|
|
*
|
|
* where:
|
|
* Addr-type register length (1,2 or 4 bytes)
|
|
* Address absolute address of the register
|
|
* value value to be stored in the register
|
|
*/
|
|
|
|
#define __ASSEMBLY__
|
|
#include <config.h>
|
|
#include "asm/arch-mx6/mx6-ddr.h"
|
|
#include "asm/arch-mx6/iomux.h"
|
|
#include "asm/arch-mx6/crm_regs.h"
|
|
|
|
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
|
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_CAS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_RAS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_RESET, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
|
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
|
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
|
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
|
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
|
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030
|
|
DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A
|
|
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x03340338
|
|
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x0334032C
|
|
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4036383C
|
|
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x2E384038
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
|
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00020036
|
|
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
|
DATA 4, MX6_MMDC_P0_MDCFG0, 0xB8BE7955
|
|
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF328F64
|
|
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
|
DATA 4, MX6_MMDC_P0_MDMISC, 0x00011740
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
|
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
|
DATA 4, MX6_MMDC_P0_MDOR, 0x00BE1023
|
|
DATA 4, MX6_MMDC_P0_MDASP, 0x00000047
|
|
DATA 4, MX6_MMDC_P0_MDCTL, 0x85190000
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00888032
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008031
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x19408030
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
|
DATA 4, MX6_MMDC_P0_MDREF, 0x00007800
|
|
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007
|
|
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
|
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
|
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
|
|
|
/* set the default clock gate to save power */
|
|
DATA 4, CCM_CCGR0, 0x00C03F3F
|
|
DATA 4, CCM_CCGR1, 0x0030FC03
|
|
DATA 4, CCM_CCGR2, 0x0FFFC000
|
|
DATA 4, CCM_CCGR3, 0x3FF00000
|
|
DATA 4, CCM_CCGR4, 0xFFFFF300
|
|
DATA 4, CCM_CCGR5, 0x0F0000F3
|
|
DATA 4, CCM_CCGR6, 0x00000FFF
|
|
|
|
/* enable AXI cache for VDOA/VPU/IPU */
|
|
DATA 4 MX6_IOMUXC_GPR4 0xF00000CF
|
|
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
|
DATA 4 MX6_IOMUXC_GPR6 0x007F007F
|
|
DATA 4 MX6_IOMUXC_GPR7 0x007F007F
|