mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
8ec293e063
H616 is very similar to H6 so most of the infrastructure can be reused. However, two big differences are that it doesn't have functional SRAM A2 which is usually used for TF-A and it doesn't have ARISC co-processor. It also needs bigger SPL size - 48 KiB. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
82 lines
2.4 KiB
C
82 lines
2.4 KiB
C
/*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_CPU_SUN50I_H6_H
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#define _SUNXI_CPU_SUN50I_H6_H
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#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS
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#define SUNXI_SRAM_C_BASE 0x00028000
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#define SUNXI_SRAM_A2_BASE 0x00100000
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#define SUNXI_DE3_BASE 0x01000000
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#define SUNXI_SS_BASE 0x01904000
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#define SUNXI_EMCE_BASE 0x01905000
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#define SUNXI_SRAMC_BASE 0x03000000
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#define SUNXI_CCM_BASE 0x03001000
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#define SUNXI_DMA_BASE 0x03002000
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/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */
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#define SUNXI_SIDC_BASE 0x03006000
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#define SUNXI_SID_BASE 0x03006200
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#define SUNXI_TIMER_BASE 0x03009000
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#define SUNXI_PIO_BASE 0x0300B000
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#define SUNXI_PSI_BASE 0x0300C000
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#define SUNXI_GIC400_BASE 0x03020000
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#define SUNXI_IOMMU_BASE 0x030F0000
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#ifdef CONFIG_MACH_SUN50I_H6
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#define SUNXI_DRAM_COM_BASE 0x04002000
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#define SUNXI_DRAM_CTL0_BASE 0x04003000
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#define SUNXI_DRAM_PHY0_BASE 0x04005000
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#endif
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#define SUNXI_NFC_BASE 0x04011000
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#define SUNXI_MMC0_BASE 0x04020000
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#define SUNXI_MMC1_BASE 0x04021000
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#define SUNXI_MMC2_BASE 0x04022000
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#ifdef CONFIG_MACH_SUN50I_H616
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#define SUNXI_DRAM_COM_BASE 0x047FA000
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#define SUNXI_DRAM_CTL0_BASE 0x047FB000
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#define SUNXI_DRAM_PHY0_BASE 0x04800000
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#endif
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#define SUNXI_UART0_BASE 0x05000000
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#define SUNXI_UART1_BASE 0x05000400
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#define SUNXI_UART2_BASE 0x05000800
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#define SUNXI_UART3_BASE 0x05000C00
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#define SUNXI_TWI0_BASE 0x05002000
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#define SUNXI_TWI1_BASE 0x05002400
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#define SUNXI_TWI2_BASE 0x05002800
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#define SUNXI_TWI3_BASE 0x05002C00
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#define SUNXI_SPI0_BASE 0x05010000
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#define SUNXI_SPI1_BASE 0x05011000
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#define SUNXI_GMAC_BASE 0x05020000
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#define SUNXI_USB0_BASE 0x05100000
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#define SUNXI_XHCI_BASE 0x05200000
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#define SUNXI_USB3_BASE 0x05311000
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#define SUNXI_PCIE_BASE 0x05400000
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#define SUNXI_HDMI_BASE 0x06000000
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#define SUNXI_TCON_TOP_BASE 0x06510000
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#define SUNXI_TCON_LCD0_BASE 0x06511000
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#define SUNXI_TCON_TV0_BASE 0x06515000
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#define SUNXI_RTC_BASE 0x07000000
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#define SUNXI_R_CPUCFG_BASE 0x07000400
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#define SUNXI_PRCM_BASE 0x07010000
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#define SUNXI_R_WDOG_BASE 0x07020400
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#define SUNXI_R_PIO_BASE 0x07022000
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#define SUNXI_R_UART_BASE 0x07080000
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#define SUNXI_R_TWI_BASE 0x07081400
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#ifndef __ASSEMBLY__
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void sunxi_board_init(void);
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void sunxi_reset(void);
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int sunxi_get_sid(unsigned int *sid);
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#endif
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#endif /* _SUNXI_CPU_SUN9I_H */
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