mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
700a0c648d
Old, obsolete and duplicated code was cleaned up and replace by the new partitioning method. There are two possible approaches now: * define a single, static partition * use mtdparts command line option and dynamic partitioning Default is static partitioning.
426 lines
13 KiB
C
426 lines
13 KiB
C
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifndef __ASSEMBLY__
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#include <galileo/core.h>
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#endif
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#include "../board/evb64260/local.h"
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_EVB64260 1 /* this is an EVB64260 board */
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#define CFG_GT_6426x GT_64260 /* with a 64260 system controller */
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#define CONFIG_BAUDRATE 38400 /* console baudrate = 38400 */
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#undef CONFIG_ECC /* enable ECC support */
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/* #define CONFIG_EVB64260_750CX 1 */ /* Support the EVB-64260-750CX Board */
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/* which initialization functions to call for this board */
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_BOARD_EARLY_INIT_F 1
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#ifndef CONFIG_EVB64260_750CX
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#define CFG_BOARD_NAME "EVB64260"
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#else
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#define CFG_BOARD_NAME "EVB64260-750CX"
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#endif
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#define CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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/*
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* The following defines let you select what serial you want to use
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* for your console driver.
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*
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* what to do:
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* to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
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* cable onto the second DUART channel, change the CFG_DUART port from 1
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* to 0 below.
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*
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* to use the MPSC, #define CONFIG_MPSC. If you have wired up another
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* mpsc channel, change CONFIG_MPSC_PORT to the desired value.
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*/
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#define CONFIG_MPSC
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#define CONFIG_MPSC_PORT 0
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#define CONFIG_NET_MULTI /* attempt all available adapters */
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/* define this if you want to enable GT MAC filtering */
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#define CONFIG_GT_USE_MAC_HASH_TABLE
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#undef CONFIG_ETHER_PORT_MII /* use RMII */
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#if 1
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#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
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#else
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#endif
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#undef CONFIG_BOOTARGS
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#define CONFIG_BOOTCOMMAND \
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"bootp && " \
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"setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:" \
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"$netmask:$hostname:eth0:none; && " \
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"bootm"
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#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
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#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_ALTIVEC /* undef to disable */
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#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
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CONFIG_BOOTP_BOOTFILESIZE)
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV)
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#include <cmd_confdefs.h>
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */
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#define CFG_LOAD_ADDR 0x00300000 /* default load address */
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#define CFG_HZ 1000 /* decr freq: 1ms ticks */
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#define CFG_BUS_HZ 100000000 /* 100 MHz */
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#define CFG_BUS_CLK CFG_BUS_HZ
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#ifdef CONFIG_EVB64260_750CX
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#define CONFIG_750CX
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#define CFG_BROKEN_CL2
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#endif
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area
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*/
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#define CFG_INIT_RAM_ADDR 0x40000000
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#define CFG_INIT_RAM_END 0x1000
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#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_RAM_LOCK
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xfff00000
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#define CFG_RESET_ADDRESS 0xfff00100
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE CFG_FLASH_BASE
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#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
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/* areas to map different things with the GT in physical space */
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#define CFG_DRAM_BANKS 4
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#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
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/* What to put in the bats. */
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#define CFG_MISC_REGION_BASE 0xf0000000
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/* Peripheral Device section */
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#define CFG_GT_REGS 0xf8000000
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#define CFG_DEV_BASE 0xfc000000
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#define CFG_DEV0_SPACE CFG_DEV_BASE
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#define CFG_DEV1_SPACE (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
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#define CFG_DEV2_SPACE (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
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#define CFG_DEV3_SPACE (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
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#define CFG_DEV0_SIZE _8M /* evb64260 sram @ 0xfc00.0000 */
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#define CFG_DEV1_SIZE _8M /* evb64260 rtc @ 0xfc80.0000 */
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#define CFG_DEV2_SIZE _16M /* evb64260 duart @ 0xfd00.0000 */
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#define CFG_DEV3_SIZE _16M /* evb64260 flash @ 0xfe00.0000 */
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#define CFG_DEV0_PAR 0x20205093
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#define CFG_DEV1_PAR 0xcfcfffff
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#define CFG_DEV2_PAR 0xc0059bd4
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#define CFG_8BIT_BOOT_PAR 0xc00b5e7c
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#define CFG_32BIT_BOOT_PAR 0xc4a8241c
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/* c 4 a 8 2 4 1 c */
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/* 33 22|2222|22 22|111 1|11 11|1 1 | | */
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/* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
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/* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
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/* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
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#if 0 /* Wrong?? NTL */
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#define CFG_MPP_CONTROL_0 0x53541717 /* InitAct EOT[4] DBurst TCEn[1] */
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/* DMAAck[1:0] GNT0[1:0] */
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#else
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#define CFG_MPP_CONTROL_0 0x53547777 /* InitAct EOT[4] DBurst TCEn[1] */
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/* REQ0[1:0] GNT0[1:0] */
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#endif
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#define CFG_MPP_CONTROL_1 0x44009911 /* TCEn[4] TCTcnt[4] GPP[13:12] */
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/* DMAReq[4] DMAAck[4] WDNMI WDE */
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#if 0 /* Wrong?? NTL */
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#define CFG_MPP_CONTROL_2 0x40091818 /* TCTcnt[0] GPP[22:21] BClkIn */
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/* DMAAck[1:0] GNT1[1:0] */
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#else
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#define CFG_MPP_CONTROL_2 0x40098888 /* TCTcnt[0] */
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/* GPP[22] (RS232IntB or PCI1Int) */
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/* GPP[21] (RS323IntA) */
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/* BClkIn */
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/* REQ1[1:0] GNT1[1:0] */
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#endif
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#if 0 /* Wrong?? NTL */
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# define CFG_MPP_CONTROL_3 0x00090066 /* GPP[31:29] BClkOut0 */
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/* GPP[27:26] Int[1:0] */
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#else
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# define CFG_MPP_CONTROL_3 0x22090066 /* MREQ MGNT */
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/* GPP[29] (PCI1Int) */
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/* BClkOut0 */
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/* GPP[27] (PCI0Int) */
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/* GPP[26] (RtcInt or PCI1Int) */
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/* CPUInt[25:24] */
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#endif
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# define CFG_SERIAL_PORT_MUX 0x00000102 /* 0=hiZ 1=MPSC0 2=ETH 0 and 2 RMII */
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#if 0 /* Wrong?? - NTL */
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# define CFG_GPP_LEVEL_CONTROL 0x000002c6
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#else
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# define CFG_GPP_LEVEL_CONTROL 0x2c600000 /* 0010 1100 0110 0000 */
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/* gpp[29] */
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/* gpp[27:26] */
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/* gpp[22:21] */
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# define CFG_SDRAM_CONFIG 0xd8e18200 /* 0x448 */
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/* idmas use buffer 1,1
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comm use buffer 0
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pci use buffer 1,1
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cpu use buffer 0
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normal load (see also ifdef HVL)
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standard SDRAM (see also ifdef REG)
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non staggered refresh */
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/* 31:26 25 23 20 19 18 16 */
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/* 110110 00 111 0 0 00 1 */
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/* refresh_count=0x200
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phisical interleaving disable
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virtual interleaving enable */
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/* 15 14 13:0 */
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/* 1 0 0x200 */
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#endif
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#define CFG_DUART_IO CFG_DEV2_SPACE
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#define CFG_DUART_CHAN 1 /* channel to use for console */
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#define CFG_INIT_CHAN1
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#define CFG_INIT_CHAN2
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#define SRAM_BASE CFG_DEV0_SPACE
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#define SRAM_SIZE 0x00100000 /* 1 MB of sram */
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
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#define PCI_HOST_FORCE 1 /* configure as pci host */
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#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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/* PCI MEMORY MAP section */
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#define CFG_PCI0_MEM_BASE 0x80000000
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#define CFG_PCI0_MEM_SIZE _128M
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#define CFG_PCI1_MEM_BASE 0x88000000
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#define CFG_PCI1_MEM_SIZE _128M
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#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
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#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
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/* PCI I/O MAP section */
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#define CFG_PCI0_IO_BASE 0xfa000000
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#define CFG_PCI0_IO_SIZE _16M
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#define CFG_PCI1_IO_BASE 0xfb000000
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#define CFG_PCI1_IO_SIZE _16M
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#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
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#define CFG_PCI0_IO_SPACE_PCI 0x00000000
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#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
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#define CFG_PCI1_IO_SPACE_PCI 0x00000000
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/*
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* NS16550 Configuration
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*/
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#define CFG_NS16550
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#define CFG_NS16550_REG_SIZE -4
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#define CFG_NS16550_CLK 3686400
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#define CFG_NS16550_COM1 (CFG_DUART_IO + 0)
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#define CFG_NS16550_COM2 (CFG_DUART_IO + 0x20)
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/*----------------------------------------------------------------------
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* Initial BAT mappings
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*/
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/* NOTES:
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* 1) GUARDED and WRITE_THRU not allowed in IBATS
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* 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
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*/
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/* SDRAM */
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#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
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#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT0U CFG_IBAT0U
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/* init ram */
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#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
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#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
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#define CFG_DBAT1L CFG_IBAT1L
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#define CFG_DBAT1U CFG_IBAT1U
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/* PCI0, PCI1 in one BAT */
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#define CFG_IBAT2L BATL_NO_ACCESS
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#define CFG_IBAT2U CFG_DBAT2U
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#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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/* GT regs, bootrom, all the devices, PCI I/O */
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#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
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#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
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#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
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#define CFG_DBAT3U CFG_IBAT3U
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/* I2C speed and slave address (for compatability) defaults */
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#define CFG_I2C_SPEED 400000
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#define CFG_I2C_SLAVE 0x7F
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/* I2C addresses for the two DIMM SPD chips */
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#ifndef CONFIG_EVB64260_750CX
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#define DIMM0_I2C_ADDR 0x56
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#define DIMM1_I2C_ADDR 0x54
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#else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
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#define DIMM0_I2C_ADDR 0x54
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#define DIMM1_I2C_ADDR 0x54
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#endif
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#define CFG_EXTRA_FLASH_DEVICE DEVICE3 /* extra flash at device 3 */
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#define CFG_EXTRA_FLASH_WIDTH 4 /* 32 bit */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_CFI 1
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x10000
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#define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
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#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* L2CR setup -- make sure this is right for your board!
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* look in include/74xx_7xx.h for the defines used here
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*/
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#define CFG_L2
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#ifdef CONFIG_750CX
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#define L2_INIT 0
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#else
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#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
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L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
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#endif
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#define L2_ENABLE (L2_INIT | L2CR_L2E)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CFG_BOARD_ASM_INIT 1
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#endif /* __CONFIG_H */
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