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59041a5084
Update MPU frequencies and voltages as per the latest DM[1] dated: OCT 2011 Revised APRIL 2016, Section 5.4. Below is the consolidated data: MPU values for PG 2.0 and later(Package ZCZ and ZCE): ------------------------------------------------------- | | ZCZ | ZCE | |-------------------------------------------------------| | | VDD[V] | ARM [MHz] | VDD[V] | ARM [MHz] | |-------|----------|------------|----------|------------| | NITRO | 1.325 | 1000 | NA | NA | |-------|----------|------------|----------|------------| | TURBO | 1.26 | 800 | NA | NA | |-------|----------|------------|----------|------------| |OPP120 | 1.20 | 720 | NA | NA | |-------|----------|------------|----------|------------| |OPP100 | 1.10 | 600 | 1.10 | 600 | |-------|----------|------------|----------|------------| | OPP50 | 0.95 | 300 | 0.95 | 300 | ------------------------------------------------------- There is no eFuse blown on PG1.0 Silicons due to which there is no way to detect the maximum frequencies supported. So default to OPP100 for which both frequency and voltages are common on both the packages. [1] http://www.ti.com/lit/ds/symlink/am3356.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
79 lines
2.6 KiB
C
79 lines
2.6 KiB
C
/*
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* (C) Copyright 2011-2013
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* For more details, please see the TRM at http://www.ti.com/product/tps65910
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*/
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#ifndef __POWER_TPS65910_H__
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#define __POWER_TPS65910_H__
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#define MPU 0
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#define CORE 1
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#define TPS65910_SR_I2C_ADDR 0x12
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#define TPS65910_CTRL_I2C_ADDR 0x2D
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/* PMIC Register offsets */
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enum {
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TPS65910_VDD1_REG = 0x21,
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TPS65910_VDD1_OP_REG = 0x22,
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TPS65910_VDD2_REG = 0x24,
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TPS65910_VDD2_OP_REG = 0x25,
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TPS65910_DEVCTRL_REG = 0x3F,
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};
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/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */
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#define TPS65910_VGAIN_SEL_MASK (0x3 << 6)
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#define TPS65910_ILMAX_MASK (0x1 << 5)
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#define TPS65910_TSTEP_MASK (0x7 << 2)
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#define TPS65910_ST_MASK (0x3)
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#define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6)
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#define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6)
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#define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6)
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#define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6)
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#define TPS65910_REG_ILMAX_1_0_A (0x0 << 5)
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#define TPS65910_REG_ILMAX_1_5_A (0x1 << 5)
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#define TPS65910_REG_TSTEP_ (0x0 << 2)
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#define TPS65910_REG_TSTEP_12_5 (0x1 << 2)
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#define TPS65910_REG_TSTEP_9_4 (0x2 << 2)
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#define TPS65910_REG_TSTEP_7_5 (0x3 << 2)
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#define TPS65910_REG_TSTEP_6_25 (0x4 << 2)
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#define TPS65910_REG_TSTEP_4_7 (0x5 << 2)
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#define TPS65910_REG_TSTEP_3_12 (0x6 << 2)
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#define TPS65910_REG_TSTEP_2_5 (0x7 << 2)
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#define TPS65910_REG_ST_OFF (0x0)
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#define TPS65910_REG_ST_ON_HI_POW (0x1)
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#define TPS65910_REG_ST_OFF_1 (0x2)
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#define TPS65910_REG_ST_ON_LOW_POW (0x3)
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/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */
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#define TPS65910_OP_REG_SEL (0x7F)
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#define TPS65910_OP_REG_CMD_MASK (0x1 << 7)
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#define TPS65910_OP_REG_CMD_OP (0x0 << 7)
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#define TPS65910_OP_REG_CMD_SR (0x1 << 7)
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#define TPS65910_OP_REG_SEL_MASK (0x7F)
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#define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */
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#define TPS65910_OP_REG_SEL_1_1_0 (0x2B) /* 1.1000 V */
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#define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */
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#define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */
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#define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */
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#define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */
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/* Device control register . (DEVCTRL_REG) */
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#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4)
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#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4)
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#define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4)
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int tps65910_set_i2c_control(void);
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int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel);
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#endif /* __POWER_TPS65910_H__ */
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