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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
It is good practice to include common.h as the first header. This ensures that required features like the DECLARE_GLOBAL_DATA_PTR macro, configuration options and common types are available. Fix up some files which currently don't do this. This is necessary because driver model will soon start using global data and configuration in the dm/read.h header file, included via dm.h. The gd->fdt_blob value will be used to access the device tree and CONFIG options will be used to determine whether to support inline functions in the header file. Signed-off-by: Simon Glass <sjg@chromium.org>
323 lines
7.1 KiB
C
323 lines
7.1 KiB
C
/*
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* LPC32xxGPIO driver
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*
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* (C) Copyright 2014 DENX Software Engineering GmbH
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* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-lpc32xx/cpu.h>
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#include <asm/arch-lpc32xx/gpio.h>
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#include <asm-generic/gpio.h>
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#include <dm.h>
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/**
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* LPC32xx GPIOs work in banks but are non-homogeneous:
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* - each bank holds a different number of GPIOs
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* - some GPIOs are input/ouput, some input only, some output only;
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* - some GPIOs have different meanings as an input and as an output;
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* - some GPIOs are controlled on a given port and bit index, but
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* read on another one.
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*
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* In order to keep this code simple, GPIOS are considered here as
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* homogeneous and linear, from 0 to 159.
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*
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* ** WARNING #1 **
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*
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* Client code is responsible for properly using valid GPIO numbers,
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* including cases where a single physical GPIO has differing numbers
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* for setting its direction, reading it and/or writing to it.
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*
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* ** WARNING #2 **
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*
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* Please read NOTE in description of lpc32xx_gpio_get_function().
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*/
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#define LPC32XX_GPIOS 160
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struct lpc32xx_gpio_priv {
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struct gpio_regs *regs;
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/* GPIO FUNCTION: SEE WARNING #2 */
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signed char function[LPC32XX_GPIOS];
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};
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/**
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* We have 4 GPIO ports of 32 bits each
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*
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* Port mapping offset (32 bits each):
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* - Port 0: 0
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* - Port 1: 32
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* - Port 2: 64
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* - Port 3: GPO / GPIO (output): 96
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* - Port 3: GPI: 128
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*/
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#define MAX_GPIO 160
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#define GPIO_TO_PORT(gpio) ((gpio / 32) & 7)
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#define GPIO_TO_RANK(gpio) (gpio % 32)
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#define GPIO_TO_MASK(gpio) (1 << (gpio % 32))
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/**
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* Configure a GPIO number 'offset' as input
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*/
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static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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int port, mask;
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_regs *regs = gpio_priv->regs;
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port = GPIO_TO_PORT(offset);
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mask = GPIO_TO_MASK(offset);
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switch (port) {
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case 0:
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writel(mask, ®s->p0_dir_clr);
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break;
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case 1:
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writel(mask, ®s->p1_dir_clr);
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break;
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case 2:
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/* ports 2 and 3 share a common direction */
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writel(mask, ®s->p2_p3_dir_clr);
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break;
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case 3:
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/* Setup direction only for GPIO_xx. */
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if ((mask >= 25) && (mask <= 30))
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writel(mask, ®s->p2_p3_dir_clr);
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break;
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case 4:
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/* GPI_xx; nothing to do. */
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break;
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default:
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return -1;
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}
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/* GPIO FUNCTION: SEE WARNING #2 */
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gpio_priv->function[offset] = GPIOF_INPUT;
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return 0;
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}
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/**
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* Get the value of a GPIO
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*/
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static int lpc32xx_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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int port, rank, mask, value;
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_regs *regs = gpio_priv->regs;
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port = GPIO_TO_PORT(offset);
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switch (port) {
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case 0:
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value = readl(®s->p0_inp_state);
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break;
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case 1:
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value = readl(®s->p1_inp_state);
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break;
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case 2:
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value = readl(®s->p2_inp_state);
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break;
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case 3:
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/* Read GPO_xx and GPIO_xx (as output) using p3_outp_state. */
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value = readl(®s->p3_outp_state);
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break;
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case 4:
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/* Read GPI_xx and GPIO_xx (as input) using p3_inp_state. */
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value = readl(®s->p3_inp_state);
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break;
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default:
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return -1;
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}
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rank = GPIO_TO_RANK(offset);
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mask = GPIO_TO_MASK(offset);
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return (value & mask) >> rank;
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}
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/**
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* Set a GPIO
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*/
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static int gpio_set(struct udevice *dev, unsigned gpio)
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{
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int port, mask;
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_regs *regs = gpio_priv->regs;
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port = GPIO_TO_PORT(gpio);
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mask = GPIO_TO_MASK(gpio);
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switch (port) {
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case 0:
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writel(mask, ®s->p0_outp_set);
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break;
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case 1:
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writel(mask, ®s->p1_outp_set);
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break;
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case 2:
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writel(mask, ®s->p2_outp_set);
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break;
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case 3:
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writel(mask, ®s->p3_outp_set);
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break;
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case 4:
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/* GPI_xx; invalid. */
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default:
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return -1;
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}
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return 0;
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}
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/**
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* Clear a GPIO
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*/
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static int gpio_clr(struct udevice *dev, unsigned gpio)
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{
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int port, mask;
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_regs *regs = gpio_priv->regs;
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port = GPIO_TO_PORT(gpio);
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mask = GPIO_TO_MASK(gpio);
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switch (port) {
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case 0:
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writel(mask, ®s->p0_outp_clr);
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break;
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case 1:
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writel(mask, ®s->p1_outp_clr);
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break;
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case 2:
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writel(mask, ®s->p2_outp_clr);
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break;
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case 3:
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writel(mask, ®s->p3_outp_clr);
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break;
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case 4:
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/* GPI_xx; invalid. */
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default:
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return -1;
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}
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return 0;
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}
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/**
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* Set the value of a GPIO
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*/
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static int lpc32xx_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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if (value)
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return gpio_set(dev, offset);
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else
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return gpio_clr(dev, offset);
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}
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/**
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* Configure a GPIO number 'offset' as output with given initial value.
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*/
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static int lpc32xx_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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int port, mask;
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_regs *regs = gpio_priv->regs;
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port = GPIO_TO_PORT(offset);
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mask = GPIO_TO_MASK(offset);
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switch (port) {
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case 0:
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writel(mask, ®s->p0_dir_set);
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break;
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case 1:
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writel(mask, ®s->p1_dir_set);
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break;
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case 2:
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/* ports 2 and 3 share a common direction */
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writel(mask, ®s->p2_p3_dir_set);
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break;
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case 3:
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/* Setup direction only for GPIO_xx. */
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if ((mask >= 25) && (mask <= 30))
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writel(mask, ®s->p2_p3_dir_set);
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break;
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case 4:
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/* GPI_xx; invalid. */
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default:
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return -1;
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}
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/* GPIO FUNCTION: SEE WARNING #2 */
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gpio_priv->function[offset] = GPIOF_OUTPUT;
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return lpc32xx_gpio_set_value(dev, offset, value);
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}
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/**
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* GPIO functions are supposed to be computed from their current
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* configuration, but that's way too complicated in LPC32XX. A simpler
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* approach is used, where the GPIO functions are cached in an array.
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* When the GPIO is in use, its function is either "input" or "output"
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* depending on its direction, otherwise its function is "unknown".
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*
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* ** NOTE **
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*
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* THIS APPROACH WAS CHOSEN DU TO THE COMPLEX NATURE OF THE LPC32XX
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* GPIOS; DO NOT TAKE THIS AS AN EXAMPLE FOR NEW CODE.
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*/
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static int lpc32xx_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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return gpio_priv->function[offset];
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}
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static const struct dm_gpio_ops gpio_lpc32xx_ops = {
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.direction_input = lpc32xx_gpio_direction_input,
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.direction_output = lpc32xx_gpio_direction_output,
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.get_value = lpc32xx_gpio_get_value,
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.set_value = lpc32xx_gpio_set_value,
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.get_function = lpc32xx_gpio_get_function,
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};
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static int lpc32xx_gpio_probe(struct udevice *dev)
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{
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struct lpc32xx_gpio_priv *gpio_priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev->uclass_priv;
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if (dev_of_offset(dev) == -1) {
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/* Tell the uclass how many GPIOs we have */
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uc_priv->gpio_count = LPC32XX_GPIOS;
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}
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/* set base address for GPIO registers */
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gpio_priv->regs = (struct gpio_regs *)GPIO_BASE;
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/* all GPIO functions are unknown until requested */
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/* GPIO FUNCTION: SEE WARNING #2 */
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memset(gpio_priv->function, GPIOF_UNKNOWN, sizeof(gpio_priv->function));
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return 0;
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}
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U_BOOT_DRIVER(gpio_lpc32xx) = {
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.name = "gpio_lpc32xx",
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.id = UCLASS_GPIO,
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.ops = &gpio_lpc32xx_ops,
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.probe = lpc32xx_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct lpc32xx_gpio_priv),
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};
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