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https://github.com/brain-hackers/u-boot-brain
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191c008a21
The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_MRCCACHE_H
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#define _ASM_ARCH_MRCCACHE_H
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#define MRC_DATA_ALIGN 0x1000
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#define MRC_DATA_SIGNATURE (('M' << 0) | ('R' << 8) | ('C' << 16) | \
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('D'<<24))
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__packed struct mrc_data_container {
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u32 signature; /* "MRCD" */
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u32 data_size; /* Size of the 'data' field */
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u32 checksum; /* IP style checksum */
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u32 reserved; /* For header alignment */
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u8 data[0]; /* Variable size, platform/run time dependent */
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};
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struct fmap_entry;
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struct spi_flash;
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/**
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* mrccache_find_current() - find the latest MRC cache record
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*
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* This searches the MRC cache region looking for the latest record to use
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* for setting up SDRAM
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*
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* @entry: Information about the position and size of the MRC cache
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* @return pointer to latest record, or NULL if none
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*/
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struct mrc_data_container *mrccache_find_current(struct fmap_entry *entry);
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/**
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* mrccache_update() - update the MRC cache with a new record
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*
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* This writes a new record to the end of the MRC cache. If the new record is
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* the same as the latest record then the write is skipped
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*
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* @sf: SPI flash to write to
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* @entry: Position and size of MRC cache in SPI flash
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* @cur: Record to write
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* @return 0 if updated, -EEXIST if the record is the same as the latest
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* record, other error if SPI write failed
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*/
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int mrccache_update(struct spi_flash *sf, struct fmap_entry *entry,
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struct mrc_data_container *cur);
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#endif
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