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8d67c3685e
T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC. It works in two mode: standalone mode and PCIe endpoint mode. T2080PCIe-RDB Feature Overview ------------------------------ Processor: - T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz DDR Memory: - Single memory controller capable of supporting DDR3 and DDR3-LP devices - 72bit 4GB DDR3-LP SODIMM in slot Ethernet interfaces: - Two 10M/100M/1G RGMII ports on-board - Two 10Gbps SFP+ ports on-board - Two 10Gbps Base-T ports on-board Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes 16 lanes configuration: - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2) - SerDes-2 Lane G-H: to SATA1 & SATA2 IFC/Local Bus: - NOR: 128MB 16-bit NOR flash - NAND: 512MB 8-bit NAND flash - CPLD: for system controlling with programable header on-board eSPI: - 64MB N25Q512 SPI flash USB: - Two USB2.0 ports with internal PHY (both Type-A) PCIe: - One PCIe x4 gold-finger - One PCIe x4 connector - One PCIe x2 end-point device (C293 Crypto co-processor) SATA: - Two SATA 2.0 ports on-board SDHC: - support a TF-card on-board I2C: - Four I2C controllers. UART: - Dual 4-pins UART serial ports Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
43 lines
1.5 KiB
C
43 lines
1.5 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPLD register set of T2080RDB board-specific.
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*/
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struct cpld_data {
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u8 chip_id1; /* 0x00 - Chip ID1 register */
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u8 chip_id2; /* 0x01 - Chip ID2 register */
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u8 hw_ver; /* 0x02 - Hardware Revision Register */
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u8 sw_ver; /* 0x03 - Software Revision register */
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u8 res0[12]; /* 0x04 - 0x0F - not used */
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u8 reset_ctl; /* 0x10 - Reset control Register */
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u8 flash_csr; /* 0x11 - Flash control and status register */
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u8 thermal_csr; /* 0x12 - Thermal control and status register */
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u8 led_csr; /* 0x13 - LED control and status register */
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u8 sfp_csr; /* 0x14 - SFP+ control and status register */
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u8 misc_csr; /* 0x15 - Misc control and status register */
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u8 boot_or; /* 0x16 - Boot config override register */
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u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
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u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
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} cpld_data_t;
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u8 cpld_read(unsigned int reg);
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void cpld_write(unsigned int reg, u8 value);
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#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
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#define CPLD_WRITE(reg, value) \
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cpld_write(offsetof(struct cpld_data, reg), value)
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/* CPLD on IFC */
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#define CPLD_LBMAP_MASK 0x3F
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#define CPLD_BANK_SEL_MASK 0x07
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#define CPLD_BANK_OVERRIDE 0x40
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#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
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#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
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#define CPLD_LBMAP_RESET 0xFF
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#define CPLD_LBMAP_SHIFT 0x03
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#define CPLD_BOOT_SEL 0x80
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