mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
![Andre Przywara](/assets/img/avatar_default.png)
If a board DT describes a cd-gpios property, but also marks the storage as non-removable, we must ignore the GPIO (as Linux does). Teach the DM_MMC part of the Allwinner MMC driver about the non-removable DT property, to fix DM_MMC access on the SoPine and Pine64-LTS board. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
751 lines
18 KiB
C
751 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Aaron <leafy.myeh@allwinnertech.com>
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*
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* MMC driver for allwinner sunxi platform.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <clk.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc.h>
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#include <asm-generic/gpio.h>
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#ifdef CONFIG_DM_MMC
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struct sunxi_mmc_variant {
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u16 mclk_offset;
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};
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#endif
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struct sunxi_mmc_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct sunxi_mmc_priv {
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unsigned mmc_no;
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uint32_t *mclkreg;
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unsigned fatal_err;
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struct gpio_desc cd_gpio; /* Change Detect GPIO */
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int cd_inverted; /* Inverted Card Detect */
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struct sunxi_mmc *reg;
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struct mmc_config cfg;
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#ifdef CONFIG_DM_MMC
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const struct sunxi_mmc_variant *variant;
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#endif
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};
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#if !CONFIG_IS_ENABLED(DM_MMC)
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/* support 4 mmc hosts */
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struct sunxi_mmc_priv mmc_host[4];
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static int sunxi_mmc_getcd_gpio(int sdc_no)
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{
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switch (sdc_no) {
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case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
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case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
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case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
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case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
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}
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return -EINVAL;
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}
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static int mmc_resource_init(int sdc_no)
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{
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struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int cd_pin, ret = 0;
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debug("init mmc %d resource\n", sdc_no);
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switch (sdc_no) {
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case 0:
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priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
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priv->mclkreg = &ccm->sd0_clk_cfg;
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break;
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case 1:
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priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
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priv->mclkreg = &ccm->sd1_clk_cfg;
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break;
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case 2:
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priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
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priv->mclkreg = &ccm->sd2_clk_cfg;
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break;
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#ifdef SUNXI_MMC3_BASE
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case 3:
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priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
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priv->mclkreg = &ccm->sd3_clk_cfg;
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break;
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#endif
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default:
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printf("Wrong mmc number %d\n", sdc_no);
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return -1;
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}
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priv->mmc_no = sdc_no;
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cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
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if (cd_pin >= 0) {
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ret = gpio_request(cd_pin, "mmc_cd");
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if (!ret) {
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sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
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ret = gpio_direction_input(cd_pin);
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}
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}
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return ret;
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}
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#endif
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static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
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{
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unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
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bool new_mode = true;
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bool calibrate = false;
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u32 val = 0;
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if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
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new_mode = false;
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/* A83T support new mode only on eMMC */
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if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
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new_mode = false;
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#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
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calibrate = true;
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#endif
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if (hz <= 24000000) {
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pll = CCM_MMC_CTRL_OSCM24;
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pll_hz = 24000000;
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} else {
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#ifdef CONFIG_MACH_SUN9I
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pll = CCM_MMC_CTRL_PLL_PERIPH0;
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pll_hz = clock_get_pll4_periph0();
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#elif defined(CONFIG_MACH_SUN50I_H6)
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pll = CCM_MMC_CTRL_PLL6X2;
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pll_hz = clock_get_pll6() * 2;
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#else
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pll = CCM_MMC_CTRL_PLL6;
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pll_hz = clock_get_pll6();
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#endif
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}
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div = pll_hz / hz;
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if (pll_hz % hz)
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div++;
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n = 0;
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while (div > 16) {
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n++;
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div = (div + 1) / 2;
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}
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if (n > 3) {
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printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
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hz);
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return -1;
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}
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/* determine delays */
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if (hz <= 400000) {
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oclk_dly = 0;
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sclk_dly = 0;
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} else if (hz <= 25000000) {
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oclk_dly = 0;
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sclk_dly = 5;
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#ifdef CONFIG_MACH_SUN9I
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} else if (hz <= 52000000) {
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oclk_dly = 5;
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sclk_dly = 4;
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} else {
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/* hz > 52000000 */
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oclk_dly = 2;
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sclk_dly = 4;
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#else
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} else if (hz <= 52000000) {
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oclk_dly = 3;
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sclk_dly = 4;
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} else {
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/* hz > 52000000 */
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oclk_dly = 1;
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sclk_dly = 4;
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#endif
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}
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if (new_mode) {
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#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
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#ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
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val = CCM_MMC_CTRL_MODE_SEL_NEW;
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#endif
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setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
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#endif
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} else if (!calibrate) {
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/*
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* Use hardcoded delay values if controller doesn't support
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* calibration
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*/
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val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
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CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
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}
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writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
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CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
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debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
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priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
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return 0;
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}
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static int mmc_update_clk(struct sunxi_mmc_priv *priv)
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{
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unsigned int cmd;
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unsigned timeout_msecs = 2000;
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unsigned long start = get_timer(0);
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cmd = SUNXI_MMC_CMD_START |
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SUNXI_MMC_CMD_UPCLK_ONLY |
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SUNXI_MMC_CMD_WAIT_PRE_OVER;
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writel(cmd, &priv->reg->cmd);
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while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
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if (get_timer(start) > timeout_msecs)
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return -1;
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}
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/* clock update sets various irq status bits, clear these */
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writel(readl(&priv->reg->rint), &priv->reg->rint);
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return 0;
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}
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static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
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{
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unsigned rval = readl(&priv->reg->clkcr);
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/* Disable Clock */
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rval &= ~SUNXI_MMC_CLK_ENABLE;
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writel(rval, &priv->reg->clkcr);
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if (mmc_update_clk(priv))
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return -1;
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/* Set mod_clk to new rate */
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if (mmc_set_mod_clk(priv, mmc->clock))
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return -1;
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/* Clear internal divider */
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rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
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writel(rval, &priv->reg->clkcr);
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#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
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/* A64 supports calibration of delays on MMC controller and we
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* have to set delay of zero before starting calibration.
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* Allwinner BSP driver sets a delay only in the case of
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* using HS400 which is not supported by mainline U-Boot or
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* Linux at the moment
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*/
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writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
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#endif
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/* Re-enable Clock */
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rval |= SUNXI_MMC_CLK_ENABLE;
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writel(rval, &priv->reg->clkcr);
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if (mmc_update_clk(priv))
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return -1;
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return 0;
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}
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static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
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struct mmc *mmc)
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{
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debug("set ios: bus_width: %x, clock: %d\n",
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mmc->bus_width, mmc->clock);
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/* Change clock first */
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if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
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priv->fatal_err = 1;
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return -EINVAL;
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}
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/* Change bus width */
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if (mmc->bus_width == 8)
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writel(0x2, &priv->reg->width);
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else if (mmc->bus_width == 4)
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writel(0x1, &priv->reg->width);
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else
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writel(0x0, &priv->reg->width);
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return 0;
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}
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int sunxi_mmc_core_init(struct mmc *mmc)
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{
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struct sunxi_mmc_priv *priv = mmc->priv;
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/* Reset controller */
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writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
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udelay(1000);
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return 0;
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}
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#endif
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static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
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struct mmc_data *data)
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{
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const int reading = !!(data->flags & MMC_DATA_READ);
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const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
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SUNXI_MMC_STATUS_FIFO_FULL;
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unsigned i;
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unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
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unsigned byte_cnt = data->blocksize * data->blocks;
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unsigned timeout_msecs = byte_cnt >> 8;
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unsigned long start;
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if (timeout_msecs < 2000)
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timeout_msecs = 2000;
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/* Always read / write data through the CPU */
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setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
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start = get_timer(0);
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for (i = 0; i < (byte_cnt >> 2); i++) {
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while (readl(&priv->reg->status) & status_bit) {
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if (get_timer(start) > timeout_msecs)
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return -1;
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}
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if (reading)
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buff[i] = readl(&priv->reg->fifo);
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else
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writel(buff[i], &priv->reg->fifo);
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}
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return 0;
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}
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static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
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uint timeout_msecs, uint done_bit, const char *what)
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{
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unsigned int status;
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unsigned long start = get_timer(0);
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do {
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status = readl(&priv->reg->rint);
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if ((get_timer(start) > timeout_msecs) ||
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(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
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debug("%s timeout %x\n", what,
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status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
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return -ETIMEDOUT;
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}
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} while (!(status & done_bit));
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return 0;
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}
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static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
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struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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unsigned int cmdval = SUNXI_MMC_CMD_START;
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unsigned int timeout_msecs;
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int error = 0;
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unsigned int status = 0;
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unsigned int bytecnt = 0;
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if (priv->fatal_err)
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return -1;
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if (cmd->resp_type & MMC_RSP_BUSY)
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debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
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if (cmd->cmdidx == 12)
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return 0;
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if (!cmd->cmdidx)
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cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
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if (cmd->resp_type & MMC_RSP_PRESENT)
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cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
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if (cmd->resp_type & MMC_RSP_136)
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cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
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if (cmd->resp_type & MMC_RSP_CRC)
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cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
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if (data) {
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if ((u32)(long)data->dest & 0x3) {
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error = -1;
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goto out;
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}
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cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
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if (data->flags & MMC_DATA_WRITE)
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cmdval |= SUNXI_MMC_CMD_WRITE;
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if (data->blocks > 1)
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cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
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writel(data->blocksize, &priv->reg->blksz);
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writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
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}
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debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
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cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
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writel(cmd->cmdarg, &priv->reg->arg);
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if (!data)
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writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
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/*
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* transfer data and check status
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* STATREG[2] : FIFO empty
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* STATREG[3] : FIFO full
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*/
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if (data) {
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int ret = 0;
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bytecnt = data->blocksize * data->blocks;
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debug("trans data %d bytes\n", bytecnt);
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writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
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ret = mmc_trans_data_by_cpu(priv, mmc, data);
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if (ret) {
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error = readl(&priv->reg->rint) &
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SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
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error = -ETIMEDOUT;
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goto out;
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}
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}
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error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
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"cmd");
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if (error)
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goto out;
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if (data) {
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timeout_msecs = 120;
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debug("cacl timeout %x msec\n", timeout_msecs);
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error = mmc_rint_wait(priv, mmc, timeout_msecs,
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data->blocks > 1 ?
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SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
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SUNXI_MMC_RINT_DATA_OVER,
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"data");
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if (error)
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goto out;
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}
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if (cmd->resp_type & MMC_RSP_BUSY) {
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unsigned long start = get_timer(0);
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timeout_msecs = 2000;
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do {
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status = readl(&priv->reg->status);
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if (get_timer(start) > timeout_msecs) {
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debug("busy timeout\n");
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error = -ETIMEDOUT;
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goto out;
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}
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} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
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}
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = readl(&priv->reg->resp3);
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cmd->response[1] = readl(&priv->reg->resp2);
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cmd->response[2] = readl(&priv->reg->resp1);
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cmd->response[3] = readl(&priv->reg->resp0);
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debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
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cmd->response[3], cmd->response[2],
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cmd->response[1], cmd->response[0]);
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} else {
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cmd->response[0] = readl(&priv->reg->resp0);
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debug("mmc resp 0x%08x\n", cmd->response[0]);
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}
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out:
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if (error < 0) {
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writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
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mmc_update_clk(priv);
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}
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writel(0xffffffff, &priv->reg->rint);
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writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
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&priv->reg->gctrl);
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return error;
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}
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#if !CONFIG_IS_ENABLED(DM_MMC)
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static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
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{
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struct sunxi_mmc_priv *priv = mmc->priv;
|
|
|
|
return sunxi_mmc_set_ios_common(priv, mmc);
|
|
}
|
|
|
|
static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
|
|
struct mmc_data *data)
|
|
{
|
|
struct sunxi_mmc_priv *priv = mmc->priv;
|
|
|
|
return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
|
|
}
|
|
|
|
static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
|
|
{
|
|
struct sunxi_mmc_priv *priv = mmc->priv;
|
|
int cd_pin;
|
|
|
|
cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
|
|
if (cd_pin < 0)
|
|
return 1;
|
|
|
|
return !gpio_get_value(cd_pin);
|
|
}
|
|
|
|
static const struct mmc_ops sunxi_mmc_ops = {
|
|
.send_cmd = sunxi_mmc_send_cmd_legacy,
|
|
.set_ios = sunxi_mmc_set_ios_legacy,
|
|
.init = sunxi_mmc_core_init,
|
|
.getcd = sunxi_mmc_getcd_legacy,
|
|
};
|
|
|
|
struct mmc *sunxi_mmc_init(int sdc_no)
|
|
{
|
|
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
|
|
struct mmc_config *cfg = &priv->cfg;
|
|
int ret;
|
|
|
|
memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
|
|
|
|
cfg->name = "SUNXI SD/MMC";
|
|
cfg->ops = &sunxi_mmc_ops;
|
|
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
cfg->host_caps = MMC_MODE_4BIT;
|
|
#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
|
|
if (sdc_no == 2)
|
|
cfg->host_caps = MMC_MODE_8BIT;
|
|
#endif
|
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
|
cfg->f_min = 400000;
|
|
cfg->f_max = 52000000;
|
|
|
|
if (mmc_resource_init(sdc_no) != 0)
|
|
return NULL;
|
|
|
|
/* config ahb clock */
|
|
debug("init mmc %d clock and io\n", sdc_no);
|
|
#if !defined(CONFIG_MACH_SUN50I_H6)
|
|
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
|
|
|
|
#ifdef CONFIG_SUNXI_GEN_SUN6I
|
|
/* unassert reset */
|
|
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
|
|
#endif
|
|
#if defined(CONFIG_MACH_SUN9I)
|
|
/* sun9i has a mmc-common module, also set the gate and reset there */
|
|
writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
|
|
SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
|
|
#endif
|
|
#else /* CONFIG_MACH_SUN50I_H6 */
|
|
setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
|
|
/* unassert reset */
|
|
setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
|
|
#endif
|
|
ret = mmc_set_mod_clk(priv, 24000000);
|
|
if (ret)
|
|
return NULL;
|
|
|
|
return mmc_create(cfg, priv);
|
|
}
|
|
#else
|
|
|
|
static int sunxi_mmc_set_ios(struct udevice *dev)
|
|
{
|
|
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
|
|
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
|
|
|
|
return sunxi_mmc_set_ios_common(priv, &plat->mmc);
|
|
}
|
|
|
|
static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
|
struct mmc_data *data)
|
|
{
|
|
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
|
|
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
|
|
|
|
return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
|
|
}
|
|
|
|
static int sunxi_mmc_getcd(struct udevice *dev)
|
|
{
|
|
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
|
|
|
|
if (dm_gpio_is_valid(&priv->cd_gpio)) {
|
|
int cd_state = dm_gpio_get_value(&priv->cd_gpio);
|
|
|
|
return cd_state ^ priv->cd_inverted;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static const struct dm_mmc_ops sunxi_mmc_ops = {
|
|
.send_cmd = sunxi_mmc_send_cmd,
|
|
.set_ios = sunxi_mmc_set_ios,
|
|
.get_cd = sunxi_mmc_getcd,
|
|
};
|
|
|
|
static int sunxi_mmc_probe(struct udevice *dev)
|
|
{
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
|
|
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
|
|
struct reset_ctl_bulk reset_bulk;
|
|
struct clk gate_clk;
|
|
struct mmc_config *cfg = &plat->cfg;
|
|
struct ofnode_phandle_args args;
|
|
u32 *ccu_reg;
|
|
int bus_width, ret;
|
|
|
|
cfg->name = dev->name;
|
|
bus_width = dev_read_u32_default(dev, "bus-width", 1);
|
|
|
|
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
cfg->host_caps = 0;
|
|
if (bus_width == 8)
|
|
cfg->host_caps |= MMC_MODE_8BIT;
|
|
if (bus_width >= 4)
|
|
cfg->host_caps |= MMC_MODE_4BIT;
|
|
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
|
|
|
cfg->f_min = 400000;
|
|
cfg->f_max = 52000000;
|
|
|
|
priv->reg = (void *)dev_read_addr(dev);
|
|
priv->variant =
|
|
(const struct sunxi_mmc_variant *)dev_get_driver_data(dev);
|
|
|
|
/* We don't have a sunxi clock driver so find the clock address here */
|
|
ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
|
|
1, &args);
|
|
if (ret)
|
|
return ret;
|
|
ccu_reg = (u32 *)ofnode_get_addr(args.node);
|
|
|
|
priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
|
|
priv->mclkreg = (void *)ccu_reg +
|
|
(priv->variant->mclk_offset + (priv->mmc_no * 4));
|
|
|
|
ret = clk_get_by_name(dev, "ahb", &gate_clk);
|
|
if (!ret)
|
|
clk_enable(&gate_clk);
|
|
|
|
ret = reset_get_bulk(dev, &reset_bulk);
|
|
if (!ret)
|
|
reset_deassert_bulk(&reset_bulk);
|
|
|
|
ret = mmc_set_mod_clk(priv, 24000000);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* This GPIO is optional */
|
|
if (!dev_read_bool(dev, "non-removable") &&
|
|
!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
|
|
GPIOD_IS_IN)) {
|
|
int cd_pin = gpio_get_number(&priv->cd_gpio);
|
|
|
|
sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
|
|
}
|
|
|
|
/* Check if card detect is inverted */
|
|
priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
|
|
|
|
upriv->mmc = &plat->mmc;
|
|
|
|
/* Reset controller */
|
|
writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
|
|
udelay(1000);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sunxi_mmc_bind(struct udevice *dev)
|
|
{
|
|
struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
static const struct sunxi_mmc_variant sun4i_a10_variant = {
|
|
.mclk_offset = 0x88,
|
|
};
|
|
|
|
static const struct sunxi_mmc_variant sun9i_a80_variant = {
|
|
.mclk_offset = 0x410,
|
|
};
|
|
|
|
static const struct sunxi_mmc_variant sun50i_h6_variant = {
|
|
.mclk_offset = 0x830,
|
|
};
|
|
|
|
static const struct udevice_id sunxi_mmc_ids[] = {
|
|
{
|
|
.compatible = "allwinner,sun4i-a10-mmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun5i-a13-mmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun7i-a20-mmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun8i-a83t-emmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun9i-a80-mmc",
|
|
.data = (ulong)&sun9i_a80_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-mmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-a64-emmc",
|
|
.data = (ulong)&sun4i_a10_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-h6-mmc",
|
|
.data = (ulong)&sun50i_h6_variant,
|
|
},
|
|
{
|
|
.compatible = "allwinner,sun50i-h6-emmc",
|
|
.data = (ulong)&sun50i_h6_variant,
|
|
},
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(sunxi_mmc_drv) = {
|
|
.name = "sunxi_mmc",
|
|
.id = UCLASS_MMC,
|
|
.of_match = sunxi_mmc_ids,
|
|
.bind = sunxi_mmc_bind,
|
|
.probe = sunxi_mmc_probe,
|
|
.ops = &sunxi_mmc_ops,
|
|
.platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
|
|
.priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
|
|
};
|
|
#endif
|