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![Siva Durga Prasad Paladugu](/assets/img/avatar_default.png)
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
318 lines
7.8 KiB
C
318 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012-2013, Xilinx, Michal Simek
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*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com
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*/
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/*
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* Xilinx FPGA support
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*/
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#include <common.h>
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#include <fpga.h>
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#include <virtex2.h>
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#include <spartan2.h>
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#include <spartan3.h>
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#include <zynqpl.h>
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/* Local Static Functions */
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static int xilinx_validate(xilinx_desc *desc, char *fn);
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/* ------------------------------------------------------------------------- */
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int fpga_is_partial_data(int devnum, size_t img_len)
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{
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const fpga_desc * const desc = fpga_get_desc(devnum);
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xilinx_desc *desc_xilinx = desc->devdesc;
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/* Check datasize against FPGA size */
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if (img_len >= desc_xilinx->size)
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return 0;
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/* datasize is smaller, must be partial data */
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return 1;
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}
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int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
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bitstream_type bstype)
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{
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unsigned int length;
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unsigned int swapsize;
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unsigned char *dataptr;
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unsigned int i;
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const fpga_desc *desc;
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xilinx_desc *xdesc;
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dataptr = (unsigned char *)fpgadata;
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/* Find out fpga_description */
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desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
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/* Assign xilinx device description */
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xdesc = desc->devdesc;
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/* skip the first bytes of the bitsteam, their meaning is unknown */
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length = (*dataptr << 8) + *(dataptr + 1);
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dataptr += 2;
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dataptr += length;
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/* get design name (identifier, length, string) */
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length = (*dataptr << 8) + *(dataptr + 1);
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dataptr += 2;
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if (*dataptr++ != 0x61) {
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debug("%s: Design name id not recognized in bitstream\n",
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__func__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr + 1);
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dataptr += 2;
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printf(" design filename = \"%s\"\n", dataptr);
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dataptr += length;
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/* get part number (identifier, length, string) */
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if (*dataptr++ != 0x62) {
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printf("%s: Part number id not recognized in bitstream\n",
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__func__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr + 1);
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dataptr += 2;
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if (xdesc->name) {
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i = (ulong)strstr((char *)dataptr, xdesc->name);
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if (!i) {
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printf("%s: Wrong bitstream ID for this device\n",
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__func__);
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printf("%s: Bitstream ID %s, current device ID %d/%s\n",
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__func__, dataptr, devnum, xdesc->name);
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return FPGA_FAIL;
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}
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} else {
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printf("%s: Please fill correct device ID to xilinx_desc\n",
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__func__);
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}
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printf(" part number = \"%s\"\n", dataptr);
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dataptr += length;
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/* get date (identifier, length, string) */
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if (*dataptr++ != 0x63) {
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printf("%s: Date identifier not recognized in bitstream\n",
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__func__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr += 2;
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printf(" date = \"%s\"\n", dataptr);
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dataptr += length;
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/* get time (identifier, length, string) */
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if (*dataptr++ != 0x64) {
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printf("%s: Time identifier not recognized in bitstream\n",
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__func__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr += 2;
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printf(" time = \"%s\"\n", dataptr);
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dataptr += length;
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/* get fpga data length (identifier, length) */
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if (*dataptr++ != 0x65) {
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printf("%s: Data length id not recognized in bitstream\n",
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__func__);
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return FPGA_FAIL;
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}
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swapsize = ((unsigned int) *dataptr << 24) +
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((unsigned int) *(dataptr + 1) << 16) +
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((unsigned int) *(dataptr + 2) << 8) +
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((unsigned int) *(dataptr + 3));
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dataptr += 4;
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printf(" bytes in bitstream = %d\n", swapsize);
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return fpga_load(devnum, dataptr, swapsize, bstype);
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}
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int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
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bitstream_type bstype)
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{
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if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
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printf ("%s: Invalid device descriptor\n", __FUNCTION__);
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->load) {
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printf("%s: Missing load operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->load(desc, buf, bsize, bstype);
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}
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#if defined(CONFIG_CMD_FPGA_LOADFS)
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int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
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fpga_fs_info *fpga_fsinfo)
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{
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if (!xilinx_validate(desc, (char *)__func__)) {
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printf("%s: Invalid device descriptor\n", __func__);
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->loadfs) {
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printf("%s: Missing loadfs operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
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}
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#endif
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#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
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int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
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struct fpga_secure_info *fpga_sec_info)
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{
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if (!xilinx_validate(desc, (char *)__func__)) {
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printf("%s: Invalid device descriptor\n", __func__);
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->loads) {
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printf("%s: Missing loads operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
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}
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#endif
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int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
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{
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if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
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printf ("%s: Invalid device descriptor\n", __FUNCTION__);
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return FPGA_FAIL;
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}
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if (!desc->operations || !desc->operations->dump) {
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printf("%s: Missing dump operation\n", __func__);
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return FPGA_FAIL;
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}
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return desc->operations->dump(desc, buf, bsize);
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}
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int xilinx_info(xilinx_desc *desc)
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{
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int ret_val = FPGA_FAIL;
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if (xilinx_validate (desc, (char *)__FUNCTION__)) {
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printf ("Family: \t");
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switch (desc->family) {
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case xilinx_spartan2:
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printf ("Spartan-II\n");
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break;
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case xilinx_spartan3:
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printf ("Spartan-III\n");
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break;
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case xilinx_virtex2:
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printf ("Virtex-II\n");
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break;
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case xilinx_zynq:
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printf("Zynq PL\n");
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break;
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case xilinx_zynqmp:
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printf("ZynqMP PL\n");
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break;
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case xilinx_versal:
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printf("Versal PL\n");
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break;
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/* Add new family types here */
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default:
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printf ("Unknown family type, %d\n", desc->family);
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}
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printf ("Interface type:\t");
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switch (desc->iface) {
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case slave_serial:
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printf ("Slave Serial\n");
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break;
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case master_serial: /* Not used */
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printf ("Master Serial\n");
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break;
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case slave_parallel:
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printf ("Slave Parallel\n");
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break;
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case jtag_mode: /* Not used */
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printf ("JTAG Mode\n");
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break;
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case slave_selectmap:
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printf ("Slave SelectMap Mode\n");
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break;
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case master_selectmap:
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printf ("Master SelectMap Mode\n");
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break;
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case devcfg:
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printf("Device configuration interface (Zynq)\n");
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break;
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case csu_dma:
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printf("csu_dma configuration interface (ZynqMP)\n");
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break;
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case cfi:
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printf("CFI configuration interface (Versal)\n");
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break;
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/* Add new interface types here */
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default:
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printf ("Unsupported interface type, %d\n", desc->iface);
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}
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printf("Device Size: \t%zd bytes\n"
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"Cookie: \t0x%x (%d)\n",
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desc->size, desc->cookie, desc->cookie);
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if (desc->name)
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printf("Device name: \t%s\n", desc->name);
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if (desc->iface_fns)
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printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
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else
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printf ("No Device Function Table.\n");
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if (desc->operations && desc->operations->info)
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desc->operations->info(desc);
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ret_val = FPGA_SUCCESS;
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} else {
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printf ("%s: Invalid device descriptor\n", __FUNCTION__);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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static int xilinx_validate(xilinx_desc *desc, char *fn)
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{
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int ret_val = false;
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if (desc) {
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if ((desc->family > min_xilinx_type) &&
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(desc->family < max_xilinx_type)) {
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if ((desc->iface > min_xilinx_iface_type) &&
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(desc->iface < max_xilinx_iface_type)) {
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if (desc->size) {
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ret_val = true;
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} else
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printf ("%s: NULL part size\n", fn);
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} else
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printf ("%s: Invalid Interface type, %d\n",
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fn, desc->iface);
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} else
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printf ("%s: Invalid family type, %d\n", fn, desc->family);
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} else
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printf ("%s: NULL descriptor!\n", fn);
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return ret_val;
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}
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