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https://github.com/brain-hackers/u-boot-brain
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95b602bab5
The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
360 lines
13 KiB
ArmAsm
360 lines
13 KiB
ArmAsm
/*------------------------------------------------------------------------------+ */
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/* */
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/* This source code is dual-licensed. You may use it under the terms */
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/* of the GNU General Public License version 2, or under the license */
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/* below. */
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/* */
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/* This source code has been made available to you by IBM on an AS-IS */
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/* basis. Anyone receiving this source is licensed under IBM */
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/* copyrights to use it in any way he or she deems fit, including */
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/* copying it, modifying it, compiling it, and redistributing it either */
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/* with or without modifications. No license under IBM patents or */
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/* patent applications is to be implied by the copyright license. */
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/* */
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/* Any user of this software should understand that IBM cannot provide */
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/* technical support for this software and will not be responsible for */
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/* any consequences resulting from the use of this software. */
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/* */
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/* Any person who transfers this source code or any derivative work */
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/* must include the IBM copyright notice, this paragraph, and the */
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/* preceding two paragraphs in the transferred software. */
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/* */
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/* COPYRIGHT I B M CORPORATION 1995 */
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/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
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/*------------------------------------------------------------------------------- */
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/*----------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* */
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/*----------------------------------------------------------------------------- */
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#include <config.h>
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#include <ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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.globl ext_bus_cntlr_init
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ext_bus_cntlr_init:
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mflr r4 /* save link register */
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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mtlr r4 /* restore link register */
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addi r4,0,14 /* set ctr to 10; used to prefetch */
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mtctr r4 /* 10 cache lines to fit this function */
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/* in cache (gives us 8x10=80 instrctns) */
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..ebcloop:
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icbt r0,r3 /* prefetch cache line for addr in r3 */
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addi r3,r3,32 /* move to next cache line */
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bdnz ..ebcloop /* continue for 10 cache lines */
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/*------------------------------------------------------------------- */
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/* Delay to ensure all accesses to ROM are complete before changing */
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/* bank 0 timings. 200usec should be enough. */
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/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
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/*------------------------------------------------------------------- */
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addis r3,0,0x0
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/*----------------------------------------------------------------------- */
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/* Memory Bank 0 (Flash) initialization (from openbios) */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS0_AP@h
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ori r4,r4,CS0_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB0CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS0_CR@h
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ori r4,r4,CS0_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 1 (NVRAM/RTC) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB1AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS1_AP@h
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ori r4,r4,CS1_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB1CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS1_CR@h
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ori r4,r4,CS1_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 2 (A/D converter) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB2AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS2_AP@h
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ori r4,r4,CS2_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB2CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS2_CR@h
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ori r4,r4,CS2_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 3 (Ethernet PHY Reset) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB3AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS3_AP@h
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ori r4,r4,CS3_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB3CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS3_CR@h
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ori r4,r4,CS3_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB4AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS4_AP@h
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ori r4,r4,CS4_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB4CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS4_CR@h
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ori r4,r4,CS4_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB5AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS5_AP@h
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ori r4,r4,CS5_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB5CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS5_CR@h
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ori r4,r4,CS5_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 6 (CPU LED0) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB6AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS6_AP@h
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ori r4,r4,CS6_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB6CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS6_CR@h
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ori r4,r4,CS5_CR@l
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mtdcr EBC0_CFGDATA,r4
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/*----------------------------------------------------------------------- */
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/* Memory Bank 7 (CPU LED1) initialization */
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/*----------------------------------------------------------------------- */
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addi r4,0,PB7AP
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS7_AP@h
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ori r4,r4,CS7_AP@l
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mtdcr EBC0_CFGDATA,r4
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addi r4,0,PB7CR
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mtdcr EBC0_CFGADDR,r4
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addis r4,0,CS7_CR@h
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ori r4,r4,CS7_CR@l
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mtdcr EBC0_CFGDATA,r4
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/* addis r4,r0,FPGA_BRDC@h */
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/* ori r4,r4,FPGA_BRDC@l */
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/* lbz r3,0(r4) /###*get FPGA board control reg */
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/* eieio */
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/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */
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/* stb r3,0(r4) */
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nop /* pass2 DCR errata #8 */
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blr
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/*----------------------------------------------------------------------------- */
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/* Function: sdram_init */
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/* Description: Configures SDRAM memory banks on ERIC. */
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/* We do manually init our SDRAM. */
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/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
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/* It is assumed that a 32MB 12x8(2) SDRAM is used. */
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/*----------------------------------------------------------------------------- */
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.globl sdram_init
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sdram_init:
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mflr r31
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#ifdef CONFIG_SYS_SDRAM_MANUALLY
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/*------------------------------------------------------------------- */
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/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_B0CR
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mtdcr SDRAM0_CFGADDR,r4
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addis r4,0,MB0CF@h
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ori r4,r4,MB0CF@l
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mtdcr SDRAM0_CFGDATA,r4
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/*------------------------------------------------------------------- */
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/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_B1CR
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mtdcr SDRAM0_CFGADDR,r4
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addis r4,0,MB1CF@h
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ori r4,r4,MB1CF@l
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mtdcr SDRAM0_CFGDATA,r4
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/*------------------------------------------------------------------- */
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/* Set MB2CF for bank 2. off */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_B2CR
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mtdcr SDRAM0_CFGADDR,r4
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addis r4,0,MB2CF@h
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ori r4,r4,MB2CF@l
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mtdcr SDRAM0_CFGDATA,r4
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/*------------------------------------------------------------------- */
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/* Set MB3CF for bank 3. off */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_B3CR
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mtdcr SDRAM0_CFGADDR,r4
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addis r4,0,MB3CF@h
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ori r4,r4,MB3CF@l
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mtdcr SDRAM0_CFGDATA,r4
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/*------------------------------------------------------------------- */
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/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
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/* To set the appropriate timings, we need to know the SDRAM speed. */
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/* We can use the PLB speed since the SDRAM speed is the same as */
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/* the PLB speed. The PLB speed is the FBK divider times the */
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/* 405GP reference clock, which on the Walnut board is 33Mhz. */
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/* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
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/* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
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/* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
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/* maybe 133Mhz. */
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/*------------------------------------------------------------------- */
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mfdcr r5,CPC0_PSR /* determine FBK divider */
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/* via STRAP reg to calc PLB speed. */
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/* SDRAM speed is the same as the PLB */
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/* speed. */
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rlwinm r4,r5,4,0x3 /* get FBK divide bits */
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..chk_66:
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cmpi %cr0,0,r4,0x1
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bne ..chk_100
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addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */
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ori r6,r6,SDTR_66@l
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addis r7,0,RTR_66 /* RTR value for 66Mhz */
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b ..sdram_ok
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..chk_100:
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cmpi %cr0,0,r4,0x2
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bne ..chk_133
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addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
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ori r6,r6,SDTR_100@l
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addis r7,0,RTR_100 /* RTR value for 100Mhz */
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b ..sdram_ok
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..chk_133:
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addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
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ori r6,r6,0x4015
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addis r7,0,0x07F0 /* RTR value for 133Mhz */
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..sdram_ok:
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/*------------------------------------------------------------------- */
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/* Set SDTR1 */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_TR
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mtdcr SDRAM0_CFGADDR,r4
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mtdcr SDRAM0_CFGDATA,r6
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/*------------------------------------------------------------------- */
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/* Set RTR */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_RTR
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mtdcr SDRAM0_CFGADDR,r4
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mtdcr SDRAM0_CFGDATA,r7
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/*------------------------------------------------------------------- */
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/* Delay to ensure 200usec have elapsed since reset. Assume worst */
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/* case that the core is running 200Mhz: */
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/* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
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/*------------------------------------------------------------------- */
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addis r3,0,0x0000
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ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
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mtctr r3
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..spinlp2:
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bdnz ..spinlp2 /* spin loop */
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/*------------------------------------------------------------------- */
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/* Set memory controller options reg, MCOPT1. */
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/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
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/* read/prefetch. */
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/*------------------------------------------------------------------- */
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addi r4,0,SDRAM0_CFG
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mtdcr SDRAM0_CFGADDR,r4
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addis r4,0,0x8080 /* set DC_EN=1 */
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ori r4,r4,0x0000
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mtdcr SDRAM0_CFGDATA,r4
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/*------------------------------------------------------------------- */
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/* Delay to ensure 10msec have elapsed since reset. This is */
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/* required for the MPC952 to stabalize. Assume worst */
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/* case that the core is running 200Mhz: */
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/* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
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/* This delay should occur before accessing SDRAM. */
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/*------------------------------------------------------------------- */
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addis r3,0,0x001E
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ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
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mtctr r3
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..spinlp3:
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bdnz ..spinlp3 /* spin loop */
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#else
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/*fixme: do SDRAM Autoconfig from EEPROM here */
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#endif
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mtlr r31 /* restore lr */
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blr
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