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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
With d6a320d
we moved some clock externs out of blackfin_local.h and
into clock.h but now need to include <asm/clock.h> in more drivers to
avoid warnings.
Cc: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Tom Rini <trini@ti.com>
173 lines
3.4 KiB
C
173 lines
3.4 KiB
C
/*
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* Blackfin MUSB HCD (Host Controller Driver) for u-boot
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*
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* Copyright (c) 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm/blackfin.h>
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#include <asm/clock.h>
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#include <asm/mach-common/bits/usb.h>
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#include "musb_core.h"
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#ifndef CONFIG_USB_BLACKFIN_CLKIN
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#define CONFIG_USB_BLACKFIN_CLKIN 24
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#endif
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/* MUSB platform configuration */
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struct musb_config musb_cfg = {
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.regs = (struct musb_regs *)USB_FADDR,
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.timeout = 0x3FFFFFF,
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.musb_speed = 0,
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};
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/*
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* This function read or write data to endpoint fifo
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* Blackfin use DMA polling method to avoid buffer alignment issues
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*
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* ep - Endpoint number
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* length - Number of bytes to write to FIFO
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* fifo_data - Pointer to data buffer to be read/write
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* is_write - Flag for read or write
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*/
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void rw_fifo(u8 ep, u32 length, void *fifo_data, int is_write)
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{
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struct bfin_musb_dma_regs *regs;
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u32 val = (u32)fifo_data;
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blackfin_dcache_flush_invalidate_range(fifo_data, fifo_data + length);
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regs = (void *)USB_DMA_INTERRUPT;
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regs += ep;
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/* Setup DMA address register */
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bfin_write16(®s->addr_low, val);
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SSYNC();
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bfin_write16(®s->addr_high, val >> 16);
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SSYNC();
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/* Setup DMA count register */
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bfin_write16(®s->count_low, length);
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bfin_write16(®s->count_high, 0);
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SSYNC();
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/* Enable the DMA */
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val = (ep << 4) | DMA_ENA | INT_ENA;
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if (is_write)
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val |= DIRECTION;
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bfin_write16(®s->control, val);
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SSYNC();
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/* Wait for compelete */
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while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << ep)))
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continue;
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/* acknowledge dma interrupt */
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bfin_write_USB_DMA_INTERRUPT(1 << ep);
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SSYNC();
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/* Reset DMA */
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bfin_write16(®s->control, 0);
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SSYNC();
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}
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void write_fifo(u8 ep, u32 length, void *fifo_data)
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{
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rw_fifo(ep, length, fifo_data, 1);
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}
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void read_fifo(u8 ep, u32 length, void *fifo_data)
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{
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rw_fifo(ep, length, fifo_data, 0);
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}
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/*
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* CPU and board-specific MUSB initializations. Aliased function
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* signals caller to move on.
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*/
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static void __def_musb_init(void)
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{
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}
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void board_musb_init(void) __attribute__((weak, alias("__def_musb_init")));
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static void bfin_anomaly_init(void)
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{
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u32 revid;
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if (!ANOMALY_05000346 && !ANOMALY_05000347)
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return;
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revid = bfin_revid();
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#ifdef __ADSPBF54x__
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if (revid > 0)
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return;
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#endif
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#ifdef __ADSPBF52x__
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if (ANOMALY_BF526 && revid > 0)
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return;
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if (ANOMALY_BF527 && revid > 1)
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return;
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#endif
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if (ANOMALY_05000346) {
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bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
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SSYNC();
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}
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if (ANOMALY_05000347) {
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bfin_write_USB_APHY_CNTRL(0x0);
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SSYNC();
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}
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}
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int musb_platform_init(void)
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{
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/* board specific initialization */
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board_musb_init();
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bfin_anomaly_init();
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/* Configure PLL oscillator register */
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bfin_write_USB_PLLOSC_CTRL(0x3080 |
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((480 / CONFIG_USB_BLACKFIN_CLKIN) << 1));
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SSYNC();
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bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
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SSYNC();
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bfin_write_USB_EP_NI0_RXMAXP(64);
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SSYNC();
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bfin_write_USB_EP_NI0_TXMAXP(64);
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SSYNC();
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/* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
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bfin_write_USB_GLOBINTR(0x7);
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SSYNC();
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bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
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EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
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EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
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EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
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EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
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SSYNC();
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return 0;
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}
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/*
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* This function performs Blackfin platform specific deinitialization for usb.
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*/
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void musb_platform_deinit(void)
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{
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}
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