York Sun 316f0d0f8f powerpc: mpc85xx: Fix static TLB table for SDRAM ... Most predefined TLB tables don't have memory coherence bit set for SDRAM. This wasn't an issue before invalidate_dcache_range() function was enabled. Without the coherence bit, dcache invalidation doesn't automatically flush the cache. The coherence bit is already set when dynamic TLB table is used. For some boards with different SPL boot method, or with legacy fixed setting, this bit needs to be set in TLB files. Signed-off-by: York Sun <york.sun@nxp.com>		2017-12-06 14:54:12 -08:00
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ddr.c	Add more SPDX-License-Identifier tags	2016-01-19 08:31:21 -05:00
Kconfig
law.c
MAINTAINERS	powerpc: mpc8548cds: Update maintainer	2017-06-12 12:18:36 -07:00
Makefile
mpc8548cds.c	powerpc: mpc8548cds: Do not wrap pci_eth_init() with CONFIG_TSEC_ENET	2016-01-28 12:22:37 -06:00
tlb.c	powerpc: mpc85xx: Fix static TLB table for SDRAM	2017-12-06 14:54:12 -08:00