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![Stefan Bosch](/assets/img/avatar_default.png)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - livetree API (dev_read_...) is used instead of fdt one (fdt...). - doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt added. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
221 lines
5.4 KiB
C
221 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Pinctrl driver for Nexell SoCs
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* (C) Copyright 2016 Nexell
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* Bongyu, KOO <freestyle@nexell.co.kr>
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*
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* (C) Copyright 2019 Stefan Bosch <stefan_b@posteo.net>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include "pinctrl-nexell.h"
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#include "pinctrl-s5pxx18.h"
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DECLARE_GLOBAL_DATA_PTR;
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static void nx_gpio_set_bit(u32 *value, u32 bit, int enable)
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{
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register u32 newvalue;
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newvalue = *value;
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newvalue &= ~(1ul << bit);
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newvalue |= (u32)enable << bit;
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writel(newvalue, value);
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}
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static void nx_gpio_set_bit2(u32 *value, u32 bit, u32 bit_value)
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{
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register u32 newvalue = *value;
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newvalue = (u32)(newvalue & ~(3ul << (bit * 2)));
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newvalue = (u32)(newvalue | (bit_value << (bit * 2)));
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writel(newvalue, value);
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}
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static int nx_gpio_open_module(void *base)
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{
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writel(0xFFFFFFFF, base + GPIOX_SLEW_DISABLE_DEFAULT);
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writel(0xFFFFFFFF, base + GPIOX_DRV1_DISABLE_DEFAULT);
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writel(0xFFFFFFFF, base + GPIOX_DRV0_DISABLE_DEFAULT);
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writel(0xFFFFFFFF, base + GPIOX_PULLSEL_DISABLE_DEFAULT);
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writel(0xFFFFFFFF, base + GPIOX_PULLENB_DISABLE_DEFAULT);
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return true;
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}
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static void nx_gpio_set_pad_function(void *base, u32 pin, u32 padfunc)
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{
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u32 reg = (pin / 16) ? GPIOX_ALTFN1 : GPIOX_ALTFN0;
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nx_gpio_set_bit2(base + reg, pin % 16, padfunc);
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}
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static void nx_gpio_set_drive_strength(void *base, u32 pin, u32 drv)
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{
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nx_gpio_set_bit(base + GPIOX_DRV1, pin, (int)(((u32)drv >> 0) & 0x1));
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nx_gpio_set_bit(base + GPIOX_DRV0, pin, (int)(((u32)drv >> 1) & 0x1));
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}
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static void nx_gpio_set_pull_mode(void *base, u32 pin, u32 mode)
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{
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if (mode == nx_gpio_pull_off) {
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nx_gpio_set_bit(base + GPIOX_PULLENB, pin, false);
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nx_gpio_set_bit(base + GPIOX_PULLSEL, pin, false);
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} else {
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nx_gpio_set_bit(base + GPIOX_PULLSEL,
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pin, (mode & 1 ? true : false));
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nx_gpio_set_bit(base + GPIOX_PULLENB, pin, true);
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}
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}
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static void nx_alive_set_pullup(void *base, u32 pin, bool enable)
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{
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u32 PULLUP_MASK;
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PULLUP_MASK = (1UL << pin);
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if (enable)
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writel(PULLUP_MASK, base + ALIVE_PADPULLUPSET);
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else
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writel(PULLUP_MASK, base + ALIVE_PADPULLUPRST);
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}
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static int s5pxx18_pinctrl_gpio_init(struct udevice *dev)
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{
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struct nexell_pinctrl_priv *priv = dev_get_priv(dev);
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const struct nexell_pin_ctrl *ctrl = priv->pin_ctrl;
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unsigned long reg = priv->base;
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int i;
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for (i = 0; i < ctrl->nr_banks - 1; i++) /* except alive bank */
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nx_gpio_open_module((void *)(reg + ctrl->pin_banks[i].offset));
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return 0;
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}
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static int s5pxx18_pinctrl_alive_init(struct udevice *dev)
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{
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struct nexell_pinctrl_priv *priv = dev_get_priv(dev);
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const struct nexell_pin_ctrl *ctrl = priv->pin_ctrl;
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unsigned long reg = priv->base;
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reg += ctrl->pin_banks[ctrl->nr_banks - 1].offset;
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writel(1, reg + ALIVE_PWRGATE);
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return 0;
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}
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int s5pxx18_pinctrl_init(struct udevice *dev)
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{
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s5pxx18_pinctrl_gpio_init(dev);
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s5pxx18_pinctrl_alive_init(dev);
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return 0;
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}
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static int is_pin_alive(const char *name)
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{
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return !strncmp(name, "alive", 5);
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}
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/**
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* s5pxx18_pinctrl_set_state: configure a pin state.
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* dev: the pinctrl device to be configured.
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* config: the state to be configured.
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*/
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static int s5pxx18_pinctrl_set_state(struct udevice *dev,
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struct udevice *config)
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{
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unsigned int count, idx, pin;
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unsigned int pinfunc, pinpud, pindrv;
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unsigned long reg;
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const char *name;
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int ret;
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/*
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* refer to the following document for the pinctrl bindings
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* doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt
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*/
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count = dev_read_string_count(config, "pins");
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if (count <= 0)
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return -EINVAL;
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pinfunc = dev_read_s32_default(config, "pin-function", -1);
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pinpud = dev_read_s32_default(config, "pin-pull", -1);
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pindrv = dev_read_s32_default(config, "pin-strength", -1);
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for (idx = 0; idx < count; idx++) {
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ret = dev_read_string_index(config, "pins", idx, &name);
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if (ret)
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return ret;
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if (!name)
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continue;
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reg = pin_to_bank_base(dev, name, &pin);
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if (is_pin_alive(name)) {
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/* pin pull up/down */
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if (pinpud != -1)
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nx_alive_set_pullup((void *)reg, pin,
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pinpud & 1);
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continue;
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}
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/* pin function */
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if (pinfunc != -1)
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nx_gpio_set_pad_function((void *)reg, pin, pinfunc);
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/* pin pull up/down/off */
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if (pinpud != -1)
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nx_gpio_set_pull_mode((void *)reg, pin, pinpud);
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/* pin drive strength */
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if (pindrv != -1)
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nx_gpio_set_drive_strength((void *)reg, pin, pindrv);
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}
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return 0;
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}
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static struct pinctrl_ops s5pxx18_pinctrl_ops = {
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.set_state = s5pxx18_pinctrl_set_state,
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};
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/* pin banks of s5pxx18 pin-controller */
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static const struct nexell_pin_bank_data s5pxx18_pin_banks[] = {
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NEXELL_PIN_BANK(32, 0xA000, "gpioa"),
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NEXELL_PIN_BANK(32, 0xB000, "gpiob"),
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NEXELL_PIN_BANK(32, 0xC000, "gpioc"),
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NEXELL_PIN_BANK(32, 0xD000, "gpiod"),
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NEXELL_PIN_BANK(32, 0xE000, "gpioe"),
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NEXELL_PIN_BANK(6, 0x0800, "alive"),
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};
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const struct nexell_pin_ctrl s5pxx18_pin_ctrl[] = {
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{
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/* pin-controller data */
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.pin_banks = s5pxx18_pin_banks,
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.nr_banks = ARRAY_SIZE(s5pxx18_pin_banks),
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},
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};
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static const struct udevice_id s5pxx18_pinctrl_ids[] = {
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{ .compatible = "nexell,s5pxx18-pinctrl",
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.data = (ulong)s5pxx18_pin_ctrl },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_s5pxx18) = {
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.name = "pinctrl_s5pxx18",
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.id = UCLASS_PINCTRL,
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.of_match = s5pxx18_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct nexell_pinctrl_priv),
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.ops = &s5pxx18_pinctrl_ops,
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.probe = nexell_pinctrl_probe,
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.flags = DM_FLAG_PRE_RELOC
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};
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