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![Marek Vasut](/assets/img/avatar_default.png)
For reason unknown, recently, the DDR init code writers are really fond of hiding some small floating point operating deep in their creations. This patch removes one from the Marvell A38x code. Instead of returning size of chip as float from ddr3_get_device_size() in GiB units, return it as int in MiB units. Since this would interfere with the huge switch code in ddr3_calc_mem_cs_size(), rework the code to match the change. Before this patch, the cs_mem_size variable could have these values: ( { 16, 32 } x { 8, 16 } x { 0.01, 0.5, 1, 2, 4, 8 } ) / 8 = { 0.000000, 0.001250, 0.002500, 0.005000, 0.062500, 0.125000, 0.250000, 0.500000, 1.000000, 2.000000, 4.000000, } The switch code checked for a subset of the resulting RAM sizes, which is in range 128 MiB ... 2048 MiB. With this patch, the cs_mem_size variable can have these values: ( { 16, 32 } x { 8, 16 } x { 0, 512, 1024, 2048, 4096, 8192 } ) / 8 = { 0, 64, 128, 256, 512, 1024, 2048, 4096 } To retain previous behavior, filter out 0 MiB (invalid size), 64 MiB and 4096 MiB options. Removing the floating point stuff also saves 1.5k from text segment: clearfog : spl/u-boot-spl:all -1592 spl/u-boot-spl:text -1592 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
770 lines
19 KiB
C
770 lines
19 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <i2c.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
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static struct dlb_config ddr3_dlb_config_table[] = {
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{REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
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{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
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{DLB_AGING_REGISTER, 0x0f7f007f},
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{DLB_EVICTION_CONTROL_REG, 0x0000129f},
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{DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
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{DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
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{DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
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{DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
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{DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
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{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
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{DLB_MAIN_QUEUE_MAP, 0x00000543},
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{DLB_LINE_SPLIT, 0x00000000},
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{DLB_USER_COMMAND_REG, 0x00000000},
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{0x0, 0x0}
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};
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static struct dlb_config ddr3_dlb_config_table_a0[] = {
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{REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
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{DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
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{DLB_AGING_REGISTER, 0x0f7f007f},
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{DLB_EVICTION_CONTROL_REG, 0x0000129f},
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{DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
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{DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
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{DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
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{DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
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{DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
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{DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
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{DLB_MAIN_QUEUE_MAP, 0x00000543},
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{DLB_LINE_SPLIT, 0x00000000},
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{DLB_USER_COMMAND_REG, 0x00000000},
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{0x0, 0x0}
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};
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#if defined(CONFIG_ARMADA_38X)
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struct dram_modes {
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char *mode_name;
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u8 cpu_freq;
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u8 fab_freq;
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u8 chip_id;
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u8 chip_board_rev;
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struct reg_data *regs;
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};
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struct dram_modes ddr_modes[] = {
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#ifdef SUPPORT_STATIC_DUNIT_CONFIG
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/* Conf name, CPUFreq, Fab_freq, Chip ID, Chip/Board, MC regs*/
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#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
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{"a38x_customer_0_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID0,
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ddr3_customer_800},
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{"a38x_customer_1_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID1,
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ddr3_customer_800},
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#else
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{"a38x_533", DDR_FREQ_533, 0, 0x0, MARVELL_BOARD, ddr3_a38x_533},
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{"a38x_667", DDR_FREQ_667, 0, 0x0, MARVELL_BOARD, ddr3_a38x_667},
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{"a38x_800", DDR_FREQ_800, 0, 0x0, MARVELL_BOARD, ddr3_a38x_800},
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{"a38x_933", DDR_FREQ_933, 0, 0x0, MARVELL_BOARD, ddr3_a38x_933},
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#endif
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#endif
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};
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#endif /* defined(CONFIG_ARMADA_38X) */
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/* Translates topology map definitions to real memory size in bits */
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u32 mem_size[] = {
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ADDR_SIZE_512MB, ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB,
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ADDR_SIZE_8GB
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};
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static char *ddr_type = "DDR3";
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/*
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* Set 1 to use dynamic DUNIT configuration,
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* set 0 (supported for A380 and AC3) to configure DUNIT in values set by
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* ddr3_tip_init_specific_reg_config
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*/
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u8 generic_init_controller = 1;
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#ifdef SUPPORT_STATIC_DUNIT_CONFIG
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static u32 ddr3_get_static_ddr_mode(void);
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#endif
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static int ddr3_hws_tune_training_params(u8 dev_num);
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/* device revision */
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#define DEV_VERSION_ID_REG 0x1823c
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#define REVISON_ID_OFFS 8
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#define REVISON_ID_MASK 0xf00
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/* A38x revisions */
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#define MV_88F68XX_Z1_ID 0x0
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#define MV_88F68XX_A0_ID 0x4
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/* A39x revisions */
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#define MV_88F69XX_Z1_ID 0x2
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/*
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* sys_env_device_rev_get - Get Marvell controller device revision number
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*
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* DESCRIPTION:
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* This function returns 8bit describing the device revision as defined
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* Revision ID Register.
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*
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* INPUT:
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* None.
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*
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* OUTPUT:
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* None.
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*
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* RETURN:
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* 8bit desscribing Marvell controller revision number
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*/
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u8 sys_env_device_rev_get(void)
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{
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u32 value;
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value = reg_read(DEV_VERSION_ID_REG);
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return (value & (REVISON_ID_MASK)) >> REVISON_ID_OFFS;
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}
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/*
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* sys_env_dlb_config_ptr_get
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*
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* DESCRIPTION: defines pointer to to DLB COnfiguration table
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*
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* INPUT: none
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*
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* OUTPUT: pointer to DLB COnfiguration table
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*
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* RETURN:
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* returns pointer to DLB COnfiguration table
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*/
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struct dlb_config *sys_env_dlb_config_ptr_get(void)
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{
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#ifdef CONFIG_ARMADA_39X
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return &ddr3_dlb_config_table_a0[0];
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#else
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if (sys_env_device_rev_get() == MV_88F68XX_A0_ID)
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return &ddr3_dlb_config_table_a0[0];
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else
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return &ddr3_dlb_config_table[0];
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#endif
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}
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/*
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* sys_env_get_cs_ena_from_reg
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*
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* DESCRIPTION: Get bit mask of enabled CS
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*
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* INPUT: None
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*
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* OUTPUT: None
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*
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* RETURN:
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* Bit mask of enabled CS, 1 if only CS0 enabled,
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* 3 if both CS0 and CS1 enabled
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*/
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u32 sys_env_get_cs_ena_from_reg(void)
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{
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return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
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REG_DDR3_RANK_CTRL_CS_ENA_MASK;
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}
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static void ddr3_restore_and_set_final_windows(u32 *win)
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{
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u32 win_ctrl_reg, num_of_win_regs;
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u32 cs_ena = sys_env_get_cs_ena_from_reg();
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u32 ui;
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win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
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num_of_win_regs = 16;
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/* Return XBAR windows 4-7 or 16-19 init configuration */
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for (ui = 0; ui < num_of_win_regs; ui++)
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reg_write((win_ctrl_reg + 0x4 * ui), win[ui]);
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printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n",
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ddr_type);
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#if defined DYNAMIC_CS_SIZE_CONFIG
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if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK)
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printf("ddr3_fast_path_dynamic_cs_size_config FAILED\n");
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#else
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u32 reg, cs;
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reg = 0x1fffffe1;
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for (cs = 0; cs < MAX_CS; cs++) {
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if (cs_ena & (1 << cs)) {
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reg |= (cs << 2);
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break;
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}
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}
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/* Open fast path Window to - 0.5G */
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reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
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#endif
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}
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static int ddr3_save_and_set_training_windows(u32 *win)
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{
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u32 cs_ena;
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u32 reg, tmp_count, cs, ui;
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u32 win_ctrl_reg, win_base_reg, win_remap_reg;
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u32 num_of_win_regs, win_jump_index;
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win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
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win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
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win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
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win_jump_index = 0x10;
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num_of_win_regs = 16;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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#ifdef DISABLE_L2_FILTERING_DURING_DDR_TRAINING
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/*
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* Disable L2 filtering during DDR training
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* (when Cross Bar window is open)
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*/
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reg_write(ADDRESS_FILTERING_END_REGISTER, 0);
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#endif
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cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;
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/* Close XBAR Window 19 - Not needed */
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/* {0x000200e8} - Open Mbus Window - 2G */
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reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
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/* Save XBAR Windows 4-19 init configurations */
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for (ui = 0; ui < num_of_win_regs; ui++)
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win[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
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/* Open XBAR Windows 4-7 or 16-19 for other CS */
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reg = 0;
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tmp_count = 0;
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for (cs = 0; cs < MAX_CS; cs++) {
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if (cs_ena & (1 << cs)) {
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switch (cs) {
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case 0:
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reg = 0x0e00;
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break;
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case 1:
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reg = 0x0d00;
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break;
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case 2:
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reg = 0x0b00;
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break;
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case 3:
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reg = 0x0700;
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break;
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}
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reg |= (1 << 0);
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reg |= (SDRAM_CS_SIZE & 0xffff0000);
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reg_write(win_ctrl_reg + win_jump_index * tmp_count,
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reg);
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reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) &
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0xffff0000);
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reg_write(win_base_reg + win_jump_index * tmp_count,
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reg);
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if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR)
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reg_write(win_remap_reg +
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win_jump_index * tmp_count, 0);
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tmp_count++;
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}
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}
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return MV_OK;
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}
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/*
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* Name: ddr3_init - Main DDR3 Init function
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* Desc: This routine initialize the DDR3 MC and runs HW training.
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* Args: None.
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* Notes:
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* Returns: None.
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*/
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int ddr3_init(void)
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{
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u32 reg = 0;
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u32 soc_num;
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int status;
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u32 win[16];
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/* SoC/Board special Initializtions */
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/* Get version from internal library */
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ddr3_print_version();
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/*Add sub_version string */
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DEBUG_INIT_C("", SUB_VERSION, 1);
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/* Switching CPU to MRVL ID */
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soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
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SAR1_CPU_CORE_OFFSET;
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switch (soc_num) {
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case 0x3:
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case 0x1:
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reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
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case 0x0:
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reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
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default:
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break;
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}
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/*
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* Set DRAM Reset Mask in case detected GPIO indication of wakeup from
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* suspend i.e the DRAM values will not be overwritten / reset when
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* waking from suspend
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*/
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if (sys_env_suspend_wakeup_check() ==
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SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED) {
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reg_bit_set(REG_SDRAM_INIT_CTRL_ADDR,
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1 << REG_SDRAM_INIT_RESET_MASK_OFFS);
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}
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/*
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* Stage 0 - Set board configuration
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*/
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/* Check if DRAM is already initialized */
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if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
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(1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
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printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);
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return MV_OK;
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}
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/*
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* Stage 1 - Dunit Setup
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*/
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/* Fix read ready phases for all SOC in reg 0x15c8 */
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reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
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reg &= ~(REG_TRAINING_DEBUG_3_MASK);
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reg |= 0x4; /* Phase 0 */
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reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
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reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
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reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
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reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
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reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
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reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
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reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
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reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
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reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
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/*
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* Axi_bresp_mode[8] = Compliant,
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* Axi_addr_decode_cntrl[11] = Internal,
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* Axi_data_bus_width[0] = 128bit
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* */
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/* 0x14a8 - AXI Control Register */
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reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
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/*
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* Stage 2 - Training Values Setup
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*/
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/* Set X-BAR windows for the training sequence */
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ddr3_save_and_set_training_windows(win);
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#ifdef SUPPORT_STATIC_DUNIT_CONFIG
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/*
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* Load static controller configuration (in case dynamic/generic init
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* is not enabled
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*/
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if (generic_init_controller == 0) {
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ddr3_tip_init_specific_reg_config(0,
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ddr_modes
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[ddr3_get_static_ddr_mode
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()].regs);
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}
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#endif
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/* Tune training algo paramteres */
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status = ddr3_hws_tune_training_params(0);
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if (MV_OK != status)
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return status;
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/* Set log level for training lib */
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ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
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/* Start New Training IP */
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status = ddr3_hws_hw_training();
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if (MV_OK != status) {
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printf("%s Training Sequence - FAILED\n", ddr_type);
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return status;
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}
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/*
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* Stage 3 - Finish
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*/
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/* Restore and set windows */
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ddr3_restore_and_set_final_windows(win);
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/* Update DRAM init indication in bootROM register */
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reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
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reg_write(REG_BOOTROM_ROUTINE_ADDR,
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reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
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/* DLB config */
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ddr3_new_tip_dlb_config();
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#if defined(ECC_SUPPORT)
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if (ddr3_if_ecc_enabled())
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ddr3_new_tip_ecc_scrub();
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#endif
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printf("%s Training Sequence - Ended Successfully\n", ddr_type);
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return MV_OK;
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}
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/*
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* Name: ddr3_get_cpu_freq
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* Desc: read S@R and return CPU frequency
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* Args:
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* Notes:
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* Returns: required value
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*/
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u32 ddr3_get_cpu_freq(void)
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{
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return ddr3_tip_get_init_freq();
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}
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/*
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* Name: ddr3_get_fab_opt
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* Desc: read S@R and return CPU frequency
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* Args:
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* Notes:
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* Returns: required value
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*/
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u32 ddr3_get_fab_opt(void)
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{
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return 0; /* No fabric */
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}
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/*
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* Name: ddr3_get_static_m_cValue - Init Memory controller with
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* static parameters
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* Desc: Use this routine to init the controller without the HW training
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* procedure.
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* User must provide compatible header file with registers data.
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* Args: None.
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|
* Notes:
|
|
* Returns: None.
|
|
*/
|
|
u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1,
|
|
u32 offset2, u32 mask2)
|
|
{
|
|
u32 reg, temp;
|
|
|
|
reg = reg_read(reg_addr);
|
|
|
|
temp = (reg >> offset1) & mask1;
|
|
if (mask2)
|
|
temp |= (reg >> offset2) & mask2;
|
|
|
|
return temp;
|
|
}
|
|
|
|
/*
|
|
* Name: ddr3_get_static_ddr_mode - Init Memory controller with
|
|
* static parameters
|
|
* Desc: Use this routine to init the controller without the HW training
|
|
* procedure.
|
|
* User must provide compatible header file with registers data.
|
|
* Args: None.
|
|
* Notes:
|
|
* Returns: None.
|
|
*/
|
|
u32 ddr3_get_static_ddr_mode(void)
|
|
{
|
|
u32 chip_board_rev, i;
|
|
u32 size;
|
|
|
|
/* Valid only for A380 only, MSYS using dynamic controller config */
|
|
#ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
|
|
/*
|
|
* Customer boards select DDR mode according to
|
|
* board ID & Sample@Reset
|
|
*/
|
|
chip_board_rev = mv_board_id_get();
|
|
#else
|
|
/* Marvell boards select DDR mode according to Sample@Reset only */
|
|
chip_board_rev = MARVELL_BOARD;
|
|
#endif
|
|
|
|
size = ARRAY_SIZE(ddr_modes);
|
|
for (i = 0; i < size; i++) {
|
|
if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
|
|
(ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
|
|
(chip_board_rev == ddr_modes[i].chip_board_rev))
|
|
return i;
|
|
}
|
|
|
|
DEBUG_INIT_S("\n*** Error: ddr3_get_static_ddr_mode: No match for requested DDR mode. ***\n\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/******************************************************************************
|
|
* Name: ddr3_get_cs_num_from_reg
|
|
* Desc:
|
|
* Args:
|
|
* Notes:
|
|
* Returns:
|
|
*/
|
|
u32 ddr3_get_cs_num_from_reg(void)
|
|
{
|
|
u32 cs_ena = sys_env_get_cs_ena_from_reg();
|
|
u32 cs_count = 0;
|
|
u32 cs;
|
|
|
|
for (cs = 0; cs < MAX_CS; cs++) {
|
|
if (cs_ena & (1 << cs))
|
|
cs_count++;
|
|
}
|
|
|
|
return cs_count;
|
|
}
|
|
|
|
void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
|
|
{
|
|
u32 tmp, hclk = 200;
|
|
|
|
switch (freq_mode) {
|
|
case 4:
|
|
tmp = 1; /* DDR_400; */
|
|
hclk = 200;
|
|
break;
|
|
case 0x8:
|
|
tmp = 1; /* DDR_666; */
|
|
hclk = 333;
|
|
break;
|
|
case 0xc:
|
|
tmp = 1; /* DDR_800; */
|
|
hclk = 400;
|
|
break;
|
|
default:
|
|
*ddr_freq = 0;
|
|
*hclk_ps = 0;
|
|
break;
|
|
}
|
|
|
|
*ddr_freq = tmp; /* DDR freq define */
|
|
*hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */
|
|
|
|
return;
|
|
}
|
|
|
|
void ddr3_new_tip_dlb_config(void)
|
|
{
|
|
u32 reg, i = 0;
|
|
struct dlb_config *config_table_ptr = sys_env_dlb_config_ptr_get();
|
|
|
|
/* Write the configuration */
|
|
while (config_table_ptr[i].reg_addr != 0) {
|
|
reg_write(config_table_ptr[i].reg_addr,
|
|
config_table_ptr[i].reg_data);
|
|
i++;
|
|
}
|
|
|
|
/* Enable DLB */
|
|
reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
|
|
reg |= DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
|
|
DLB_MBUS_PREFETCH_EN | PREFETCH_N_LN_SZ_TR;
|
|
reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
|
|
}
|
|
|
|
int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
|
|
{
|
|
u32 reg, cs;
|
|
u32 mem_total_size = 0;
|
|
u32 cs_mem_size = 0;
|
|
u32 mem_total_size_c, cs_mem_size_c;
|
|
|
|
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
|
|
u32 physical_mem_size;
|
|
u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
|
|
struct hws_topology_map *tm = ddr3_get_topology_map();
|
|
#endif
|
|
|
|
/* Open fast path windows */
|
|
for (cs = 0; cs < MAX_CS; cs++) {
|
|
if (cs_ena & (1 << cs)) {
|
|
/* get CS size */
|
|
if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
|
|
return MV_FAIL;
|
|
|
|
#ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
|
|
/*
|
|
* if number of address pins doesn't allow to use max
|
|
* mem size that is defined in topology
|
|
* mem size is defined by DEVICE_MAX_DRAM_ADDRESS_SIZE
|
|
*/
|
|
physical_mem_size = mem_size
|
|
[tm->interface_params[0].memory_size];
|
|
|
|
if (ddr3_get_device_width(cs) == 16) {
|
|
/*
|
|
* 16bit mem device can be twice more - no need
|
|
* in less significant pin
|
|
*/
|
|
max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
|
|
}
|
|
|
|
if (physical_mem_size > max_mem_size) {
|
|
cs_mem_size = max_mem_size *
|
|
(ddr3_get_bus_width() /
|
|
ddr3_get_device_width(cs));
|
|
printf("Updated Physical Mem size is from 0x%x to %x\n",
|
|
physical_mem_size,
|
|
DEVICE_MAX_DRAM_ADDRESS_SIZE);
|
|
}
|
|
#endif
|
|
|
|
/* set fast path window control for the cs */
|
|
reg = 0xffffe1;
|
|
reg |= (cs << 2);
|
|
reg |= (cs_mem_size - 1) & 0xffff0000;
|
|
/*Open fast path Window */
|
|
reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
|
|
|
|
/* Set fast path window base address for the cs */
|
|
reg = ((cs_mem_size) * cs) & 0xffff0000;
|
|
/* Set base address */
|
|
reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
|
|
|
|
/*
|
|
* Since memory size may be bigger than 4G the summ may
|
|
* be more than 32 bit word,
|
|
* so to estimate the result divide mem_total_size and
|
|
* cs_mem_size by 0x10000 (it is equal to >> 16)
|
|
*/
|
|
mem_total_size_c = mem_total_size >> 16;
|
|
cs_mem_size_c = cs_mem_size >> 16;
|
|
/* if the sum less than 2 G - calculate the value */
|
|
if (mem_total_size_c + cs_mem_size_c < 0x10000)
|
|
mem_total_size += cs_mem_size;
|
|
else /* put max possible size */
|
|
mem_total_size = L2_FILTER_FOR_MAX_MEMORY_SIZE;
|
|
}
|
|
}
|
|
|
|
/* Set L2 filtering to Max Memory size */
|
|
reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size);
|
|
|
|
return MV_OK;
|
|
}
|
|
|
|
u32 ddr3_get_bus_width(void)
|
|
{
|
|
u32 bus_width;
|
|
|
|
bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >>
|
|
REG_SDRAM_CONFIG_WIDTH_OFFS;
|
|
|
|
return (bus_width == 0) ? 16 : 32;
|
|
}
|
|
|
|
u32 ddr3_get_device_width(u32 cs)
|
|
{
|
|
u32 device_width;
|
|
|
|
device_width = (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) &
|
|
(0x3 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs))) >>
|
|
(REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs);
|
|
|
|
return (device_width == 0) ? 8 : 16;
|
|
}
|
|
|
|
static int ddr3_get_device_size(u32 cs)
|
|
{
|
|
u32 device_size_low, device_size_high, device_size;
|
|
u32 data, cs_low_offset, cs_high_offset;
|
|
|
|
cs_low_offset = REG_SDRAM_ADDRESS_SIZE_OFFS + cs * 4;
|
|
cs_high_offset = REG_SDRAM_ADDRESS_SIZE_OFFS +
|
|
REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs;
|
|
|
|
data = reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR);
|
|
device_size_low = (data >> cs_low_offset) & 0x3;
|
|
device_size_high = (data >> cs_high_offset) & 0x1;
|
|
|
|
device_size = device_size_low | (device_size_high << 2);
|
|
|
|
switch (device_size) {
|
|
case 0:
|
|
return 2048;
|
|
case 2:
|
|
return 512;
|
|
case 3:
|
|
return 1024;
|
|
case 4:
|
|
return 4096;
|
|
case 5:
|
|
return 8192;
|
|
case 1:
|
|
default:
|
|
DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
|
|
/*
|
|
* Small value will give wrong emem size in
|
|
* ddr3_calc_mem_cs_size
|
|
*/
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
|
|
{
|
|
int cs_mem_size;
|
|
|
|
/* Calculate in GiB */
|
|
cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
|
|
ddr3_get_device_size(cs)) / 8;
|
|
|
|
/*
|
|
* Multiple controller bus width, 2x for 64 bit
|
|
* (SoC controller may be 32 or 64 bit,
|
|
* so bit 15 in 0x1400, that means if whole bus used or only half,
|
|
* have a differnt meaning
|
|
*/
|
|
cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
|
|
|
|
if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
|
|
DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
|
|
return MV_BAD_VALUE;
|
|
}
|
|
|
|
*cs_size = cs_mem_size << 20;
|
|
return MV_OK;
|
|
}
|
|
|
|
/*
|
|
* Name: ddr3_hws_tune_training_params
|
|
* Desc:
|
|
* Args:
|
|
* Notes: Tune internal training params
|
|
* Returns:
|
|
*/
|
|
static int ddr3_hws_tune_training_params(u8 dev_num)
|
|
{
|
|
struct tune_train_params params;
|
|
int status;
|
|
|
|
/* NOTE: do not remove any field initilization */
|
|
params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
|
|
params.ck_delay_16 = TUNE_TRAINING_PARAMS_CK_DELAY_16;
|
|
params.p_finger = TUNE_TRAINING_PARAMS_PFINGER;
|
|
params.n_finger = TUNE_TRAINING_PARAMS_NFINGER;
|
|
params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
|
|
|
|
status = ddr3_tip_tune_training_params(dev_num, ¶ms);
|
|
if (MV_OK != status) {
|
|
printf("%s Training Sequence - FAILED\n", ddr_type);
|
|
return status;
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|