mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
8cb4817d0f
Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
45 lines
778 B
C
45 lines
778 B
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/compiler.h>
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#include <asm/cache.h>
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#include <asm/mipsregs.h>
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#include <asm/reboot.h>
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void __weak _machine_restart(void)
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{
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fprintf(stderr, "*** reset failed ***\n");
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while (1)
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/* NOP */;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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_machine_restart();
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return 0;
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}
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void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
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{
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write_c0_entrylo0(low0);
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write_c0_pagemask(pagemask);
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write_c0_entrylo1(low1);
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write_c0_entryhi(hi);
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write_c0_index(index);
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tlb_write_indexed();
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}
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int arch_cpu_init(void)
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{
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mips_cache_probe();
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return 0;
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}
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