mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
ee3a55fdf0
* 'master' of git://git.denx.de/u-boot-arm: (167 commits) OMAP4/5: Change omap4_sdp, omap4_panda, omap5_evm maintainer ARM: omap3: Add CONFIG_SPL_BOARD_INIT for CONFIG_SPL_MMC_SUPPORT ARM: omap3: Set SPL stack size to 8KB, image to 54KB. arm, omap3: fix warm reset serial output on OMAP36xx/AM/DM37xx OMAP4: Set fdt_high for OMAP4 devices to enable booting with Device Tree omap4: do not enable auxiliary cores omap4: do not enable fs-usb module omap4: panda: disable uart2 pads during boot igep00x0: change mpurate from 500 to auto igep00x0: enable the use of a plain text file tegra2: trivially enable 13 mhz crystal frequency tegra: Enable keyboard for Seaboard tegra: Switch on console mux and use environment for console tegra: Add tegra keyboard driver tegra: fdt: Add keyboard definitions for Seaboard tegra: fdt: Add keyboard controller definition tegra: Add keyboard support to funcmux input: Add support for keyboard matrix decoding from an fdt input: Add generic keyboard input handler input: Add linux/input.h for key code support fdt: Add fdtdec functions to read byte array tegra: Enable LP0 on Seaboard tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: i2c: Add function to find DVC bus fdt: tegra: Add EMC node to device tree tegra: Add EMC settings for Seaboard tegra: Turn off power detect in board init tegra: Set up warmboot code on Nvidia boards tegra: Setup PMC scratch info from ap20 setup tegra: Add warmboot implementation tegra: Set up PMU for Nvidia boards tegra: Add PMU to manage power supplies tegra: Add EMC support for optimal memory timings tegra: Add header file for APB_MISC register tegra: Add tegra_get_chip_type() to detect SKU tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add crypto library for warmboot code tegra: Add functions to access low-level Osc/PLL details tegra: Move ap20.h header into arch location Add AES crypto library i2c: Add TPS6586X driver Add abs() macro to return absolute value fdt: Add function to return next compatible subnode fdt: Add function to locate an array in the device tree i.MX28: Avoid redefining serial_put[cs]() i.MX28: Check if WP detection is implemented at all i.MX28: Add battery boot components to SPL i.MX28: Reorder battery status functions in SPL i.MX28: Add LRADC init to i.MX28 SPL i.MX28: Add LRADC register definitions i.MX28: Shut down the LCD controller before reset i.MX28: Add LCDIF register definitions i.MX28: Implement boot pads sampling and reporting i.MX28: Improve passing of data from SPL to U-Boot M28EVK: Add SD update command M28EVK: Implement support for new board V2.0 FEC: Abstract out register setup MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged i.MX28: Add delay after CPU bypass is cleared spi: mxs: Allow other chip selects to work spi: mxs: Introduce spi_cs_is_valid() mx53loco: Remove unneeded gpio_set_value() mx53loco: Add CONFIG_REVISION_TAG mx53loco: Turn on VUSB regulator mx53loco: Add mc34708 support and set mx53 frequency at 1GHz pmic: dialog: Avoid name conflicts imx: Add u-boot.imx as target for ARM9 i.MX SOCs i.MX2: Include asm/types.h in arch-mx25/imx-regs.h imx: usb: There is no such register i.MX25: usb: Set PORTSCx register imx: nand: Support flash based BBT i.MX25: This architecture has a GPIO4 too i.MX25: esdhc: Add mxc_get_clock infrastructure i.MX6: mx6q_sabrelite: add SATA bindings i.MX6: add enable_sata_clock() i.MX6: Add ANATOP regulator init mx28evk: add NAND support USB: ehci-mx6: Fix broken IO access M28: Scan only first 512 MB of DRAM to avoid memory wraparound Revert "i.MX28: Enable additional DRAM address bits" M28: Enable FDT support mx53loco: Add support for 1GHz operation for DA9053-based boards mx53loco: Allow to print CPU information at a later stage mx5: Add clock config interface imx-common: Factor out get_ahb_clk() i.MX6Q: mx6qsabrelite: Add keypress support to alter boot flow mx31pdk: Allow booting a zImage kernel mx6qarm2: Allow booting a zImage kernel mx6qsabrelite: Allow booting a zImage kernel mx28evk: Allow booting a zImage kernel m28evk: Allow to booting a dt kernel mx28evk: Allow to booting a dt kernel mx6qsabrelite: No need to set the direction for GPIO3_23 again pmic: Add support for the Dialog DA9053 PMIC MX53: mx53loco: Add SATA support MX53: Add support to ESG ima3 board SATA: add driver for MX5 / MX6 SOCs MX53: add function to set SATA clock to internal SATA: check for return value from sata functions MX5: Add definitions for SATA controller NET: fec_mxc.c: Add a way to disable auto negotiation Define UART4 and UART5 base addresses EXYNOS: Change bits per pixel value proper for u-boot. EXYNOS: support TRATS board display function LCD: support S6E8AX0 amoled driver based on EXYNOS MIPI DSI EXYNOS: support EXYNOS MIPI DSI interface driver. EXYNOS: support EXYNOS framebuffer and FIMD display drivers. LCD: add data structure for EXYNOS display driver EXYNOS: add LCD and MIPI DSI clock interface. EXYNOS: definitions of system resgister and power management registers. SMDK5250: fix compiler warning misc:pmic:samsung Convert TRATS target to use MAX8997 instead of MAX8998 misc:pmic:max8997 MAX8997 support for PMIC driver TRATS: modify the trats's configuration ARM: Exynos4: ADC: Universal_C210: Enable LDO4 power line for ADC measurement EXYNOS: Rename exynos5_tzpc structure to exynos_tzpc arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT cm-t35: add I2C multi-bus support include/configs: Remove CONFIG_SYS_64BIT_STRTOUL include/configs: Remove CONFIG_SYS_64BIT_VSPRINTF omap3: Introduce weak misc_init_r omap730p2: Remove empty misc_init_r omap5912osk: Remove empty misc_init_r omap4+: Remove CONFIG_ARCH_CPU_INIT omap4: Remove CONFIG_SYS_MMC_SET_DEV OMAP3: pandora: drop console kernel argument OMAP3: pandora: revise GPIO configuration ...
226 lines
6.8 KiB
C
226 lines
6.8 KiB
C
/*
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* Copyright (C) 2011 Samsung Electronics
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* Heungjun Kim <riverful.kim@samsung.com>
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*
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* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_SAMSUNG /* in a SAMSUNG core */
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#define CONFIG_S5P /* which is in a S5P Family */
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#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
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#define CONFIG_TRATS /* working with TRATS */
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#include <asm/arch/cpu.h> /* get chip and board defs */
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Keep L2 Cache Disabled */
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#define CONFIG_SYS_L2CACHE_OFF
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x63300000
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/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
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#define CONFIG_SYS_CLK_FREQ_C210 24000000
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#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_BOARD_EARLY_INIT_F
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/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
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#define MACH_TYPE_TRATS 3928
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#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
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/* select serial console configuration */
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#define CONFIG_SERIAL_MULTI
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#define CONFIG_SERIAL2 /* use SERIAL 2 */
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#define CONFIG_BAUDRATE 115200
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/* MMC */
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#define CONFIG_GENERIC_MMC
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#define CONFIG_MMC
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#define CONFIG_S5P_SDHCI
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#define CONFIG_SDHCI
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/* PWM */
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#define CONFIG_PWM
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/* It should define before config_cmd_default.h */
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#define CONFIG_SYS_NO_FLASH
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/* Command definition */
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#include <config_cmd_default.h>
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_MISC
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_XIMG
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#undef CONFIG_CMD_CACHE
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#undef CONFIG_CMD_ONENAND
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#undef CONFIG_CMD_MTDPARTS
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#define CONFIG_CMD_MMC
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#define CONFIG_BOOTDELAY 1
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_BOOTARGS "Please use defined boot"
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#define CONFIG_BOOTCOMMAND "run mmcboot"
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
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#define CONFIG_BOOTBLOCK "10"
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#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_CONSOLE_INFO_QUIET
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"bootk=" \
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"run loaduimage; bootm 0x40007FC0\0" \
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"updatemmc=" \
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"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
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"mmc boot 0 1 1 0\0" \
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"updatebackup=" \
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"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
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"mmc boot 0 1 1 0\0" \
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"updatebootb=" \
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"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
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"lpj=lpj=3981312\0" \
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"nfsboot=" \
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"set bootargs root=/dev/nfs rw " \
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"nfsroot=${nfsroot},nolock,tcp " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:" \
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"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
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"; run bootk\0" \
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"ramfsboot=" \
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"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
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"${console} ${meminfo} " \
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"initrd=0x43000000,8M ramdisk=8192\0" \
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"mmcboot=" \
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"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
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"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
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"run loaduimage; bootm 0x40007FC0\0" \
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"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
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"boottrace=setenv opts initcall_debug; run bootcmd\0" \
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"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
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"verify=n\0" \
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"rootfstype=ext4\0" \
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"console=" CONFIG_DEFAULT_CONSOLE \
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"meminfo=crashkernel=32M@0x50000000\0" \
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"nfsroot=/nfsroot/arm\0" \
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"bootblock=" CONFIG_BOOTBLOCK "\0" \
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"mmcdev=0\0" \
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"mmcbootpart=2\0" \
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"mmcrootpart=3\0" \
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"opts=always_resume=1"
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_PROMPT "TRATS # "
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* memtest works on */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
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#define CONFIG_SYS_HZ 1000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* Stack sizes */
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#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
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/* TRATS has 2 banks of DRAM */
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#define CONFIG_NR_DRAM_BANKS 2
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#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
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#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
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#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
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#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
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#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
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#define CONFIG_SYS_MONITOR_BASE 0x00000000
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#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 4096
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#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#include <asm/arch/gpio.h>
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/*
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* I2C Settings
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*/
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#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
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#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
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#define CONFIG_SOFT_I2C
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#define CONFIG_SOFT_I2C_READ_REPEATED_START
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_MAX_I2C_BUS 7
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#define CONFIG_PMIC
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#define CONFIG_PMIC_I2C
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#define CONFIG_PMIC_MAX8997
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#define CONFIG_USB_GADGET
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#define CONFIG_USB_GADGET_S3C_UDC_OTG
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#define CONFIG_USB_GADGET_DUALSPEED
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/* LCD */
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#define CONFIG_EXYNOS_FB
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#define CONFIG_LCD
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#define CONFIG_FB_ADDR 0x52504000
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#define CONFIG_S6E8AX0
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#define CONFIG_EXYNOS_MIPI_DSIM
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1280 * 720 * 4)
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#endif /* __CONFIG_H */
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