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https://github.com/brain-hackers/u-boot-brain
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3e0529f742
Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
43 lines
1.3 KiB
C
43 lines
1.3 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* P5020 DS board configuration file
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*
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*/
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#define CONFIG_P5020DS
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#define CONFIG_PHYS_64BIT
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#define CONFIG_PPC_P5020
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#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
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#define CONFIG_MMC
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#define CONFIG_NAND_FSL_ELBC
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#define CONFIG_PCIE3
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#define CONFIG_PCIE4
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#define CONFIG_SYS_FSL_RAID_ENGINE
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#define CONFIG_SYS_DPAA_RMAN
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#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
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#include "corenet_ds.h"
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