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8ca79b2ff4
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
44 lines
1.4 KiB
C
44 lines
1.4 KiB
C
/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/gp_padctrl.h>
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#include "pinmux-config-cardhu.h"
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/*
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* Routine: pinmux_init
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* Description: Do individual peripheral pinmux configs
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*/
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void pinmux_init(void)
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{
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pinmux_config_table(tegra3_pinmux_common,
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ARRAY_SIZE(tegra3_pinmux_common));
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pinmux_config_table(unused_pins_lowpower,
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ARRAY_SIZE(unused_pins_lowpower));
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/* Initialize any non-default pad configs (APB_MISC_GP regs) */
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padgrp_config_table(cardhu_padctrl, ARRAY_SIZE(cardhu_padctrl));
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}
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