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https://github.com/brain-hackers/u-boot-brain
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14360bf059
Slim Bootloader already calibrated TSC and provides it to U-Boot. Therefore, U-Boot does not have to re-calibrate TSC. Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass TSC calibration and use the provided TSC frequency. - Get TSC frequency from performance info hob - Set tsc_base and clock_rate for tsc_timer driver Signed-off-by: Aiden Park <aiden.park@intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
59 lines
1.3 KiB
C
59 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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*/
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#include <common.h>
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#include <asm/arch/slimbootloader.h>
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* This sets tsc_base and clock_rate for early_timer and tsc_timer.
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* The performance info guid hob has all performance timestamp data, but
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* the only tsc frequency info is used for the timer driver for now.
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*
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* Slim Bootloader already calibrated TSC and provides it to U-Boot.
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* Therefore, U-Boot does not have to re-calibrate TSC.
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* Configuring tsc_base and clock_rate here makes x86 tsc_timer driver
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* bypass TSC calibration and use the provided TSC frequency.
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*/
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static void tsc_init(void)
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{
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struct sbl_performance_info *data;
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const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID;
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if (!gd->arch.hob_list)
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panic("hob list not found!");
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gd->arch.tsc_base = rdtsc();
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debug("tsc_base=0x%llx\n", gd->arch.tsc_base);
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data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid);
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if (!data) {
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debug("performance info hob not found\n");
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return;
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}
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/* frequency is in KHz, so to Hz */
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gd->arch.clock_rate = data->frequency * 1000;
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debug("freq=0x%lx\n", gd->arch.clock_rate);
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}
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int arch_cpu_init(void)
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{
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tsc_init();
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return x86_cpu_init_f();
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}
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int checkcpu(void)
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{
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return 0;
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}
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int print_cpuinfo(void)
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{
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return default_print_cpuinfo();
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}
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