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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
205 lines
4.9 KiB
C
205 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2014 Google, Inc
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* (C) Copyright 2008
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* Graeme Russ, graeme.russ@gmail.com.
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*
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* Some portions from coreboot src/mainboard/google/link/romstage.c
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* and src/cpu/intel/model_206ax/bootblock.c
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* Copyright (C) 2007-2010 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <pch.h>
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#include <asm/cpu.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/lpc_common.h>
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#include <asm/microcode.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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#include <asm/arch/model_206ax.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/sandybridge.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int set_flex_ratio_to_tdp_nominal(void)
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{
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/* Minimum CPU revision for configurable TDP support */
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if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
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return -EINVAL;
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return cpu_set_flex_ratio_to_tdp_nominal();
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}
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int arch_cpu_init(void)
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{
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post_code(POST_CPU_INIT);
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return x86_cpu_init_f();
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}
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int arch_cpu_init_dm(void)
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{
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struct pci_controller *hose;
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struct udevice *bus, *dev;
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int ret;
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post_code(0x70);
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ret = uclass_get_device(UCLASS_PCI, 0, &bus);
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post_code(0x71);
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if (ret)
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return ret;
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post_code(0x72);
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hose = dev_get_uclass_priv(bus);
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/* TODO(sjg@chromium.org): Get rid of gd->hose */
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gd->hose = hose;
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ret = uclass_first_device_err(UCLASS_LPC, &dev);
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if (ret)
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return ret;
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/*
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* We should do as little as possible before the serial console is
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* up. Perhaps this should move to later. Our next lot of init
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* happens in checkcpu() when we have a console
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*/
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ret = set_flex_ratio_to_tdp_nominal();
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if (ret)
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return ret;
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return 0;
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}
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#define PCH_EHCI0_TEMP_BAR0 0xe8000000
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#define PCH_EHCI1_TEMP_BAR0 0xe8000400
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#define PCH_XHCI_TEMP_BAR0 0xe8001000
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/*
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* Setup USB controller MMIO BAR to prevent the reference code from
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* resetting the controller.
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*
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* The BAR will be re-assigned during device enumeration so these are only
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* temporary.
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*
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* This is used to speed up the resume path.
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*/
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static void enable_usb_bar(struct udevice *bus)
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{
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pci_dev_t usb0 = PCH_EHCI1_DEV;
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pci_dev_t usb1 = PCH_EHCI2_DEV;
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pci_dev_t usb3 = PCH_XHCI_DEV;
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ulong cmd;
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/* USB Controller 1 */
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pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
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PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
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/* USB Controller 2 */
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pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
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PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
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/* USB3 Controller 1 */
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pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
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PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
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pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
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}
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int checkcpu(void)
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{
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enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
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struct udevice *dev, *lpc;
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uint32_t pm1_cnt;
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uint16_t pm1_sts;
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int ret;
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/* TODO: cmos_post_init() */
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if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
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debug("soft reset detected\n");
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boot_mode = PEI_BOOT_SOFT_RESET;
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/* System is not happy after keyboard reset... */
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debug("Issuing CF9 warm reset\n");
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reset_cpu(0);
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}
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ret = cpu_common_init();
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if (ret) {
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debug("%s: cpu_common_init() failed\n", __func__);
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return ret;
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}
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/* Check PM1_STS[15] to see if we are waking from Sx */
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pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
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/* Read PM1_CNT[12:10] to determine which Sx state */
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pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
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if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
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debug("Resume from S3 detected, but disabled.\n");
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} else {
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/*
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* TODO: An indication of life might be possible here (e.g.
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* keyboard light)
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*/
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}
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post_code(POST_EARLY_INIT);
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/* Enable SPD ROMs and DDR-III DRAM */
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ret = uclass_first_device_err(UCLASS_I2C, &dev);
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if (ret) {
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debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
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return ret;
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}
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/* Prepare USB controller early in S3 resume */
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if (boot_mode == PEI_BOOT_RESUME) {
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uclass_first_device(UCLASS_LPC, &lpc);
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enable_usb_bar(pci_get_controller(lpc->parent));
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}
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gd->arch.pei_boot_mode = boot_mode;
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return 0;
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}
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int print_cpuinfo(void)
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{
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char processor_name[CPU_MAX_NAME_LEN];
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const char *name;
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/* Print processor name */
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name = cpu_get_name(processor_name);
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printf("CPU: %s\n", name);
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post_code(POST_CPU_INFO);
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return 0;
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}
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void board_debug_uart_init(void)
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{
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/* This enables the debug UART */
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pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
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PCI_SIZE_16);
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}
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