mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
At present, for broadwell, SDRAM is always set up in U-Boot proper since the 64-bit mode (which uses SDRAM init in SPL) is not supported. Update the code to allow SDRAM init in SPL instead so that U-Boot proper can be loaded into SDRAM and run from there. This allows U-Boot to be compressed to reduce space, since it is not necessary to run it directly from flash. It could later allow us to support 64-bit U-Boot on broadwell. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2011 The Chromium Authors
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/mrc_common.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/pei_data.h>
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__weak asmlinkage void sdram_console_tx_byte(unsigned char byte)
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{
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#ifdef DEBUG
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putc(byte);
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#endif
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}
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void broadwell_fill_pei_data(struct pei_data *pei_data)
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{
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pei_data->pei_version = PEI_VERSION;
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pei_data->board_type = BOARD_TYPE_ULT;
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pei_data->pciexbar = MCFG_BASE_ADDRESS;
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pei_data->smbusbar = SMBUS_BASE_ADDRESS;
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pei_data->ehcibar = EARLY_EHCI_BAR;
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pei_data->xhcibar = EARLY_XHCI_BAR;
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pei_data->gttbar = EARLY_GTT_BAR;
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pei_data->pmbase = ACPI_BASE_ADDRESS;
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pei_data->gpiobase = GPIO_BASE_ADDRESS;
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pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
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pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
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pei_data->tx_byte = sdram_console_tx_byte;
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pei_data->ddr_refresh_2x = 1;
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}
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static void pei_data_usb2_port(struct pei_data *pei_data, int port, uint length,
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uint enable, uint oc_pin, uint location)
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{
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pei_data->usb2_ports[port].length = length;
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pei_data->usb2_ports[port].enable = enable;
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pei_data->usb2_ports[port].oc_pin = oc_pin;
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pei_data->usb2_ports[port].location = location;
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}
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static void pei_data_usb3_port(struct pei_data *pei_data, int port, uint enable,
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uint oc_pin, uint fixed_eq)
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{
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pei_data->usb3_ports[port].enable = enable;
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pei_data->usb3_ports[port].oc_pin = oc_pin;
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pei_data->usb3_ports[port].fixed_eq = fixed_eq;
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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/* DQ byte map for Samus board */
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const u8 dq_map[2][6][2] = {
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{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
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{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
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{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
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{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
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/* DQS CPU<>DRAM map for Samus board */
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const u8 dqs_map[2][8] = {
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{ 2, 0, 1, 3, 6, 4, 7, 5 },
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{ 2, 1, 0, 3, 6, 5, 4, 7 } };
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pei_data->ec_present = 1;
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/* One installed DIMM per channel */
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pei_data->dimm_channel0_disabled = 2;
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pei_data->dimm_channel1_disabled = 2;
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memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
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memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
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/* P0: HOST PORT */
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pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
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USB_PORT_BACK_PANEL);
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/* P1: HOST PORT */
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pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
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USB_PORT_BACK_PANEL);
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/* P2: RAIDEN */
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pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P3: SD CARD */
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pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P4: RAIDEN */
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pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P5: WWAN (Disabled) */
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pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
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USB_PORT_SKIP);
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/* P6: CAMERA */
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pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P7: BT */
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pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P1: HOST PORT */
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pei_data_usb3_port(pei_data, 0, 1, 0, 0);
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/* P2: HOST PORT */
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pei_data_usb3_port(pei_data, 1, 1, 1, 0);
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/* P3: RAIDEN */
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pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
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/* P4: RAIDEN */
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pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
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}
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static int broadwell_northbridge_early_init(struct udevice *dev)
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{
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/* Move earlier? */
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dm_pci_write_config32(dev, PCIEXBAR + 4, 0);
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/* 64MiB - 0-63 buses */
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dm_pci_write_config32(dev, PCIEXBAR, MCFG_BASE_ADDRESS | 4 | 1);
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dm_pci_write_config32(dev, MCHBAR, MCH_BASE_ADDRESS | 1);
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dm_pci_write_config32(dev, DMIBAR, DMI_BASE_ADDRESS | 1);
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dm_pci_write_config32(dev, EPBAR, EP_BASE_ADDRESS | 1);
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writel(EDRAM_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + EDRAMBAR);
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writel(GDXC_BASE_ADDRESS | 1, MCH_BASE_ADDRESS + GDXCBAR);
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/* Set C0000-FFFFF to access RAM on both reads and writes */
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dm_pci_write_config8(dev, PAM0, 0x30);
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dm_pci_write_config8(dev, PAM1, 0x33);
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dm_pci_write_config8(dev, PAM2, 0x33);
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dm_pci_write_config8(dev, PAM3, 0x33);
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dm_pci_write_config8(dev, PAM4, 0x33);
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dm_pci_write_config8(dev, PAM5, 0x33);
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dm_pci_write_config8(dev, PAM6, 0x33);
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/* Device enable: IGD and Mini-HD */
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dm_pci_write_config32(dev, DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
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return 0;
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}
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static int broadwell_northbridge_probe(struct udevice *dev)
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{
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if (!(gd->flags & GD_FLG_RELOC))
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return broadwell_northbridge_early_init(dev);
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return 0;
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}
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static const struct udevice_id broadwell_northbridge_ids[] = {
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{ .compatible = "intel,broadwell-northbridge" },
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{ }
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};
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U_BOOT_DRIVER(broadwell_northbridge_drv) = {
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.name = "broadwell_northbridge",
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.id = UCLASS_NORTHBRIDGE,
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.of_match = broadwell_northbridge_ids,
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.probe = broadwell_northbridge_probe,
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};
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